仿真平台内核初版 -tlib库包含<sparc arm riscv powerPC>

2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
--- a/platforms/cpus/sam_e70.repl
+++ b/platforms/cpus/sam_e70.repl
@@ -0,0 +1,49 @@
+sram: Memory.MappedMemory @ sysbus 0x20000000
+    size: 0x10000000
+
+flash: Memory.MappedMemory @ sysbus 0x0
+    size: 0x10000000
+
+usart0: UART.SAM_USART @ sysbus 0x40024000
+    IRQ -> nvic@13
+
+usart1: UART.SAM_USART @ sysbus 0x40028000
+    IRQ -> nvic@14
+
+usart2: UART.SAM_USART @ sysbus 0x4002c000
+    IRQ -> nvic@15
+
+nvic: IRQControllers.NVIC @ sysbus 0xE000E000
+    priorityMask: 0xE0
+    systickFrequency: 450000000
+    IRQ -> cpu@0
+
+cpu: CPU.CortexM @ sysbus
+    cpuType: "cortex-m7"
+    nvic: nvic
+
+rom: Memory.MappedMemory @ sysbus 0x1FFF0000
+    size: 0x10000
+
+gem: Network.CadenceGEM @ sysbus 0x40050000
+    IRQ -> nvic@39
+
+phy: Network.EthernetPhysicalLayer @ gem 0
+    Id1: 0x0007
+    Id2: 0xC0F1
+    AutoNegotiationAdvertisement: 0x00A1
+    AutoNegotiationLinkPartnerBasePageAbility: 0x0001
+
+trng: Miscellaneous.SAM_TRNG @ sysbus 0x40070000
+    // our model does not support interrupts yet, but if it did:
+    // -> nvic@57
+
+PMC_SR: Python.PythonPeripheral @ sysbus 0x400E0668
+    size: 0x4
+    initable: true
+    filename: "scripts/pydev/flipflop.py"
+
+sysbus:
+    init:
+        Tag <0x400E0940 0x4> "CIDR" 0xa1020e00
+        ApplySVD @https://dl.antmicro.com/projects/renode/svd/ATSAME70Q21.svd