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仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
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platforms/cpus/riscv_virt.repl Normal file
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dram: Memory.MappedMemory @ sysbus 0x80000000
size: 0x80000000
uart0: UART.NS16550 @ sysbus 0x10000000
IRQ -> plic@3
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32imac"
privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
hartId: 0
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x0C000000
0 -> cpu@11
numberOfSources: 52
numberOfContexts: 1
clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000
[0,1] -> cpu@[3,7]
frequency: 10000000