仿真平台内核初版 -tlib库包含<sparc arm riscv powerPC>

2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
9748 changed files with 4309137 additions and 0 deletions
--- a/platforms/cpus/opentitan-earlgrey-cw310.repl
+++ b/platforms/cpus/opentitan-earlgrey-cw310.repl
@@ -0,0 +1,12 @@
+// fpga_cw310 target uses different clock frequencies
+// https://github.com/lowRISC/opentitan/blob/2fb276797e0dcda96195b1e4617f2aac82a925f0/sw/device/lib/arch/device_fpga_cw310.c
+using "./opentitan-earlgrey.repl"
+
+cpu0:
+    PerformanceInMips: 10
+
+rv_timer:
+    frequency: 2500000
+
+timer_aon:
+    frequency: 250000