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仿真平台内核初版 -tlib库 包含<sparc arm riscv powerPC>

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liuwb
2026-02-07 20:43:43 +08:00
parent de61f9e2b0
commit b3117648be
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platforms/boards/miv-board-additional-uarts.repl Normal file
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using "./miv-board.repl"
uart_net_1: UART.MiV_CoreUART @ sysbus 0x70008000
clockFrequency: 66000000
uart_net_2: UART.MiV_CoreUART @ sysbus 0x70009000
clockFrequency: 66000000