yanchicao-yiwei-slt

2026-03-13 13:54:49 +08:00
parent 362a5c9b5d
commit 2ca0aa2bd9
5466 changed files with 2225687 additions and 187 deletions
--- a/platforms/cpus/mips32_simple.repl
+++ b/platforms/cpus/mips32_simple.repl
@@ -0,0 +1,11 @@
+// MIPS32简单测试平台
+// 包含一个MIPS CPU、内存和UART
+
+cpu: CPU.Mips @ sysbus
+    cpuType: "mips"
+
+mem: Memory.MappedMemory @ sysbus 0x80000000
+    size: 0x10000000
+
+uart: UART.LiteX_UART @ sysbus 0x10000000
+    -> cpu@0