44 lines
1.1 KiB
Plaintext
44 lines
1.1 KiB
Plaintext
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rom: Memory.MappedMemory @ { sysbus 0x0 }
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size: 0x10000
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sram: Memory.MappedMemory @ { sysbus 0x1000000 }
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size: 0x8000
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spiflash: Memory.MappedMemory @ { sysbus 0x20000000 }
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size: 0x1000000
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main_ram: Memory.MappedMemory @ { sysbus 0x40000000 }
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size: 0x10000000
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cpu: CPU.VexRiscv @ sysbus
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cpuType: "rv32im_zicsr_zifencei"
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ctrl: Miscellaneous.LiteX_SoC_Controller @ { sysbus 0x82000000 }
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uart: UART.LiteX_UART @ { sysbus 0x82002000 }
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-> cpu@0
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timer0: Timers.LiteX_Timer @ { sysbus 0x82002800 }
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-> cpu@1
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frequency: 100000000
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sysbus:
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init add:
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SilenceRange <2181050368 0x200> # ddrphy
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sysbus:
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init add:
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SilenceRange <2181052416 0x200> # sdram
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ethmac: Network.LiteX_Ethernet @ {
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sysbus 0x82006000;
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sysbus new Bus.BusMultiRegistration { address: 0xb0000000; size: 0x2000; region: "buffer" };
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sysbus new Bus.BusMultiRegistration { address: 0x82005800; size: 0x800; region: "phy" }
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}
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-> cpu@2
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ethphy: Network.EthernetPhysicalLayer @ ethmac 0
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VendorSpecific1: 0x4400 // MDIO status: 100Mbps + link up
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