367 lines
16 KiB
Plaintext
367 lines
16 KiB
Plaintext
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*** Variables ***
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${UART} sysbus.uart0
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${URI} @https://dl.antmicro.com/projects/renode
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${LINUX_PROMPT} \#${SPACE}
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# DTBs are embedded in Coreboot+Linux ROMs. Built with Coreboot v4.20.1, ATF v2.9.0, Linux v6.3 and Buildroot 2023.08-rc1.
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${COREBOOT_ARMv8A_ROM} ${URI}/coreboot-without-payload-armv8a.rom-s_16777216-b5c6df85cfb8d240d31fe3cd1d055a3106d2fadb
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${COREBOOT_ARMv8A_GICv2_ROM_LINUX} ${URI}/coreboot-linux-armv8a-gicv2.rom-s_67108864-fb2ff9ba59a83cc29deecaf79d4fd3a62196be8a
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${COREBOOT_ARMv8A_GICv3_ROM_LINUX} ${URI}/coreboot-linux-armv8a-gicv3.rom-s_67108864-2348c80d6b871b9ac1916dfe0fd590125559ef73
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${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX} ${URI}/coreboot-linux-armv8_2a-gicv3.rom-s_67108864-6643f8e84c2f6e9f8205d7f2d35142fad66cb959
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${OREBOOT_GICv2_DTB} ${URI}/aarch64-oreboot-cortex-a53-gicv2.dtb-s_1402-91c68d88d35caf827e213fed170fcda80a3a3b96
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${OREBOOT_GICv3_DTB} ${URI}/aarch64-oreboot-cortex-a53-gicv3.dtb-s_1394-6805aad03aeae232a620e6afa11d929f3a06bc95
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${OREBOOT_LINUX_BIN} ${URI}/cortex_a53-oreboot-linux-rust-shell.bin-s_67108864-9bb5a940528af703ecd716dc99e39f543e7353a7
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${UBOOT_DTB} ${URI}/cortex-a53-gicv2.dtb-s_1048576-2f0dd29f4be231d02cc1c99c7a85cf5c895b3b49
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${UBOOT_ELF} ${URI}/cortex-a53-u-boot.elf-s_7272248-e9dbaeaa70ddf928ec69f822180703c8729398a5
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${UBOOT_LINUX_IMAGE} ${URI}/cortex-a53-Image-s_12589568-b03715d3f08414d582a2467990dff7b4a7dd2213
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*** Keywords ***
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Create Machine
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[Arguments] ${gic_version}=3 ${el2_el3_disabled}=False ${gic_security_disabled}=False ${cpu_model}=cortex-a53
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Execute Command using sysbus
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Execute Command mach create
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${PLATFORM} = Get File ${CURDIR}/../../platforms/cpus/cortex-a53-gicv${gic_version}.repl
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IF "${cpu_model}" != "cortex-a53"
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${PLATFORM} = Replace String ${PLATFORM} cortex-a53 ${cpu_model}
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END
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Execute Command machine LoadPlatformDescriptionFromString """${PLATFORM}"""
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IF ${el2_el3_disabled}
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Execute Command cpu SetAvailableExceptionLevels false false
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END
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IF ${gic_security_disabled}
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Execute Command gic DisabledSecurity true
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END
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Create Terminal Tester ${UART} defaultPauseEmulation=true
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Execute Command showAnalyzer ${UART}
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Create Multicore Machine
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Execute Command include @scripts/single-node/cortex-a53-linux.resc
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Create Terminal Tester ${UART}
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Boot Linux And Login
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# Verify that SMP works
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Wait For Line On Uart SMP: Total of 4 processors activated includeUnfinishedLine=true
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Wait For Prompt On Uart buildroot login: timeout=50
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Write Line To Uart root
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Wait For Prompt On Uart ${LINUX_PROMPT}
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Configure UART For Boot Logs
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[Arguments] ${uart}
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# Set UART enable bit. The reset value is 0x300.
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Execute Command ${uart} WriteDoubleWord 0x30 0x301
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# Set 7-bit word length to hush the warning that 5-bit WLEN is unsupported.
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Execute Command ${uart} WriteDoubleWord 0x2c 0x40 #b10 << 5
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Coreboot Should Load ATF
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Wait For Line On Uart bootblock starting
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Wait For Line On Uart romstage starting
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Wait For Line On Uart ramstage starting
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Wait For Line On Uart Relocating uncompressed kernel to 0x40000000
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Wait For Line On Uart Entry Point 0x0e0a0000
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ATF Should Jump To Linux
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[Arguments] ${gic_version}=3
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Wait For Line On Uart BL31: v2.9(release):v2.9.0
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IF ${gic_version} == 2
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Wait For Line On Uart ARM GICv2 driver initialized
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ELSE
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Wait For Line On Uart GICv3 with legacy support detected.
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Wait For Line On Uart ARM GICv3 driver initialized in EL3
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END
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Wait For Line On Uart BL31: Preparing for EL3 exit to normal world
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Linux Should Print CPU Model ID
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[Arguments] ${cpu_model}=cortex-a53
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IF "${cpu_model}" == "cortex-a53"
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${cpu_model_id}= Set Variable 0x410fd034
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ELSE IF "${cpu_model}" == "cortex-a75"
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${cpu_model_id}= Set Variable 0x413fd0a1
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ELSE IF "${cpu_model}" == "cortex-a76"
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${cpu_model_id}= Set Variable 0x414fd0b1
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ELSE IF "${cpu_model}" == "cortex-a78"
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${cpu_model_id}= Set Variable 0x411fd412
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ELSE
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Fail "No ID for the given CPU: ${cpu_model}"
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END
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Wait For Line On Uart Booting Linux on physical CPU 0x0000000000 [${cpu_model_id}]
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Linux Should Print GICv2 Info
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Wait For Line On Uart GIC: Using split EOI/Deactivate mode
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Linux Should Print GICv3 Info
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Wait For Line On Uart GICv3: GIC: Using split EOI/Deactivate mode
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Wait For Line On Uart GICv3: 960 SPIs implemented
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Wait For Line On Uart GICv3: 0 Extended SPIs implemented
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Wait For Line On Uart Root IRQ handler: gic_handle_irq
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Wait For Line On Uart GICv3: GICv3 features: 16 PPIs
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Wait For Line On Uart GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
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Linux Should Run Init Process
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[Arguments] ${arch_timer_type} ${cpu_start_el} ${uart_irq} ${perfevents_counters}=False
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... ${squashfs}=False ${fuse}=False ${virtio_mmio_devices}=False ${check_rtc}=True
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Wait For Line On Uart arch_timer: cp15 timer(s) running at 62.50MHz (${arch_timer_type}).
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Wait For Line On Uart smp: Bringing up secondary CPUs ...
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Wait For Line On Uart smp: Brought up 1 node, 1 CPU
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Wait For Line On Uart SMP: Total of 1 processors activated.
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Wait For Line On Uart CPU features: detected: 32-bit EL0 Support
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Wait For Line On Uart CPU features: detected: CRC32 instructions
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Wait For Line On Uart CPU: All CPU(s) started at EL${cpu_start_el}
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Wait For Line On Uart Serial: AMBA PL011 UART driver
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Wait For Line On Uart 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = ${uart_irq}, base_baud = 0) is a PL011 rev3
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Wait For Line On Uart printk: console [ttyAMA0] enabled
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# When comparing with the actual UART output be aware the whole log is sometimes printed again at this point.
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IF ${virtio_mmio_devices}
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# Only the first of 32 was added to the platform to check if it can be successfully used to create virtio_blk device.
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# Initializing the remaining 31 results in 'Wrong magic value' logs.
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Wait For Line On Uart virtio-mmio a000200.virtio_mmio: Wrong magic value 0x00000000
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Wait For Line On uart virtio_blk virtio0: [vda] 0 512-byte logical blocks (0 B/0 B)
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END
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IF ${check_rtc}
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Wait For Line On Uart rtc-pl031 9010000.pl031: registered as rtc0
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# It can be the current date with 'machine RealTimeClockMode HostTimeUTC' but testing it here would be problematic.
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Wait For Line On Uart rtc-pl031 9010000.pl031: setting system clock to 1970-01-01
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END
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Wait For Line On Uart Freeing unused kernel memory
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# There are most probably problems with timer IRQs if the test fails to reach this line.
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Wait For Line On Uart Run /init as init process
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Linux Should Start Rust Userspace
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Wait For Line On Uart The words I got: [Literal("#")]
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Wait For Line On Uart rush: #: No such file or directory (os error 2)
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Wait For Line On Uart The words I got: [Literal("ls")]
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Wait For Line On Uart bin \ dev \ init \ proc \ sys
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Wait For Line On Uart The words I got: [Literal("exec")]
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Wait For Line On Uart The words I got: [Literal("sh")]
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Wait For Line On Uart \#> includeUnfinishedLine=true
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Write Line To Uart ls
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Wait For Line On Uart The words I got: [Literal("ls")]
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Wait For Line On Uart bin \ dev \ init \ proc \ sys
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Wait For Services And Enter Shell
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[Arguments] ${with_network}=False
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Wait For Line On Uart Starting syslogd: OK
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Wait For Line On Uart Starting klogd: OK
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Wait For Line On Uart Running sysctl: OK
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IF ${with_network}
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Wait For Line On Uart Starting network: Waiting for interface eth0 to appear timeout=16
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END
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Wait For Line On Uart Welcome to Buildroot
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Wait For Prompt On Uart buildroot login:${SPACE}
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Write Line To Uart root
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Wait For Prompt On Uart \#${SPACE}
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Shell Should Handle Basic Commands
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# Let's only match lines that don't contain any version.
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Write Line To Uart cat /etc/os-release
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Wait For Line On Uart Buildroot
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Wait For Prompt On Uart \#${SPACE}
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Write Line To Uart ls -1 /
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Wait For Line On Uart bin
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Wait For Line On Uart dev
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Wait For Line On Uart etc
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Wait For Line On Uart init
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${before}= Wait For Prompt On Uart \#${SPACE}
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Write Line To Uart sleep 1
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${after}= Wait For Prompt On Uart \#${SPACE}
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# Timestamps are in milliseconds
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Should Be True ${after.Timestamp} - ${before.Timestamp} > 1000
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Should Be True ${after.Timestamp} - ${before.Timestamp} < 1050
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Test Running Coreboot With Linux And ARM Trusted Firmware
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[Arguments] ${cpu_model} ${coreboot_rom}
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Create Machine cpu_model=${cpu_model}
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Execute Command sysbus LoadBinary ${coreboot_rom} 0x0
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Configure UART For Boot Logs ${UART}
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Coreboot Should Load ATF
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ATF Should Jump To Linux
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Linux Should Print CPU Model ID cpu_model=${cpu_model}
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Linux Should Print GICv3 Info
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Linux Should Run Init Process
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... arch_timer_type=phys
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... cpu_start_el=2
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... uart_irq=14
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... perfevents_counters=1
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... squashfs=False
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... fuse=True
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Wait For Services And Enter Shell
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Shell Should Handle Basic Commands
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*** Test Cases ***
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Test Running Coreboot Without Payload
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Create Machine
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Execute Command sysbus LoadBinary ${COREBOOT_ARMv8A_ROM} 0x0
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Configure UART For Boot Logs ${UART}
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Wait For Line On Uart bootblock starting
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Wait For Line On Uart romstage starting
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Wait For Line On Uart ARM64: Exception handlers installed.
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Wait For Line On Uart RAMDETECT: Found 1024 MiB RAM
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Wait For Line On Uart ramstage starting
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# These three messages won't be shown, e.g., if accesses close to the end of RAM fail.
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Wait For Line On Uart Timestamp - start of ramstage
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Wait For Line On Uart Writing coreboot table
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Wait For Line On Uart FMAP: area COREBOOT found
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Wait For Line On Uart Payload not loaded.
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Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A53 With GICv2
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[Tags] basic-tests
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Create Machine gic_version=2
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Execute Command sysbus LoadBinary ${COREBOOT_ARMv8A_GICv2_ROM_LINUX} 0x0
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Configure UART For Boot Logs ${UART}
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Coreboot Should Load ATF
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ATF Should Jump To Linux gic_version=2
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Linux Should Print CPU Model ID
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Linux Should Print GICv2 Info
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Linux Should Run Init Process
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... arch_timer_type=phys
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... cpu_start_el=2
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... uart_irq=14
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Wait For Services And Enter Shell
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Shell Should Handle Basic Commands
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Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A53
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Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a53 ${COREBOOT_ARMv8A_GICv3_ROM_LINUX}
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Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A75
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Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a75 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX}
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Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A76
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Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a76 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX}
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Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A78
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Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a78 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX}
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Test Running Oreboot With Linux And Rust Shell With GICv2
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Create Machine gic_version=2 el2_el3_disabled=True gic_security_disabled=True
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Execute Command sysbus LoadBinary ${OREBOOT_GICv2_DTB} 0x40000000
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Execute Command sysbus LoadBinary ${OREBOOT_LINUX_BIN} 0x0
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Configure UART For Boot Logs ${UART}
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Execute Command cpu.timer CounterFrequencyRegister 62500000
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Wait For Line On Uart Welcome to oreboot
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Wait For Line On Uart Not in EL3, jumping to payload
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Linux Should Print CPU Model ID
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# There are no details on GIC version.
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Wait For Line On Uart NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
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Wait For Line On Uart Root IRQ handler: gic_handle_irq
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Linux Should Run Init Process
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... arch_timer_type=virt
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... cpu_start_el=1
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... uart_irq=13
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... check_rtc=False
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Linux Should Start Rust Userspace
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Test Running Oreboot With Linux And Rust Shell With GICv3
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[Tags] basic-tests
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Create Machine el2_el3_disabled=True gic_security_disabled=True
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Execute Command sysbus LoadBinary ${OREBOOT_GICv3_DTB} 0x40000000
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Execute Command sysbus LoadBinary ${OREBOOT_LINUX_BIN} 0x0
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Configure UART For Boot Logs ${UART}
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Execute Command cpu.timer CounterFrequencyRegister 62500000
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Wait For Line On Uart Welcome to oreboot
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Wait For Line On Uart Not in EL3, jumping to payload
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Linux Should Print CPU Model ID
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Wait For Line On Uart NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
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Wait For Line On Uart GICv3: 960 SPIs implemented
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Wait For Line On Uart Root IRQ handler: gic_handle_irq
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Linux Should Run Init Process
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... arch_timer_type=virt
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... cpu_start_el=1
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... uart_irq=13
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... check_rtc=False
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Linux Should Start Rust Userspace
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Test Running U-Boot With Linux
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[Tags] basic-tests
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# U-Boot doesn't properly support GIC Security Extensions.
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Create Machine gic_version=2 gic_security_disabled=True
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# DeviceTree contains 32 virtio_blk/virtio_mmio devices at 0x0a000000, 0x0a000200, ..., 0x0a003e00 but
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# let's at least add one to check if it can be properly initialized. Initializing others won't succeed.
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Execute Command machine LoadPlatformDescriptionFromString "virtio0: Storage.VirtIOBlockDevice @ sysbus 0x0a000000"
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Execute Command sysbus LoadELF ${UBOOT_ELF}
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Execute Command sysbus LoadBinary ${UBOOT_DTB} 0x40000000
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Execute Command sysbus LoadBinary ${UBOOT_LINUX_IMAGE} 0x40400000
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# In U-Boot, this register is expected to be configured by a previous bootloader.
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Execute Command cpu.timer CounterFrequencyRegister 62500000
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Wait For Line On Uart U-Boot 2023.01
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Wait For Line On Uart Hit any key to stop autoboot includeUnfinishedLine=true
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Write Line To Uart
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Write Line To Uart setenv bootargs \"console=ttyAMA0 earlycon\"; booti 0x40400000 - \${fdtcontroladdr}
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Wait For Line On Uart Starting kernel ...
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Linux Should Print CPU Model ID
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Linux Should Print GICv2 Info
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Linux Should Run Init Process
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... arch_timer_type=phys
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... cpu_start_el=2
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... uart_irq=48
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... virtio_mmio_devices=True
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Wait For Services And Enter Shell with_network=True
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Shell Should Handle Basic Commands
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Should Boot And Login
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Create Multicore Machine
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Boot Linux And Login
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# Check if we see other CPUs
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Write Line To Uart nproc
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Wait For Line On Uart 4
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