50 lines
1.2 KiB
Plaintext
50 lines
1.2 KiB
Plaintext
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sram: Memory.MappedMemory @ sysbus 0x20000000
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size: 0x10000000
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flash: Memory.MappedMemory @ sysbus 0x0
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size: 0x10000000
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usart0: UART.SAM_USART @ sysbus 0x40024000
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IRQ -> nvic@13
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usart1: UART.SAM_USART @ sysbus 0x40028000
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IRQ -> nvic@14
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usart2: UART.SAM_USART @ sysbus 0x4002c000
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IRQ -> nvic@15
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nvic: IRQControllers.NVIC @ sysbus 0xE000E000
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priorityMask: 0xE0
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systickFrequency: 450000000
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IRQ -> cpu@0
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cpu: CPU.CortexM @ sysbus
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cpuType: "cortex-m7"
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nvic: nvic
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rom: Memory.MappedMemory @ sysbus 0x1FFF0000
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size: 0x10000
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gem: Network.CadenceGEM @ sysbus 0x40050000
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IRQ -> nvic@39
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phy: Network.EthernetPhysicalLayer @ gem 0
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Id1: 0x0007
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Id2: 0xC0F1
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AutoNegotiationAdvertisement: 0x00A1
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AutoNegotiationLinkPartnerBasePageAbility: 0x0001
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trng: Miscellaneous.SAM_TRNG @ sysbus 0x40070000
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// our model does not support interrupts yet, but if it did:
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// -> nvic@57
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PMC_SR: Python.PythonPeripheral @ sysbus 0x400E0668
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size: 0x4
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initable: true
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filename: "scripts/pydev/flipflop.py"
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sysbus:
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init:
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Tag <0x400E0940 0x4> "CIDR" 0xa1020e00
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ApplySVD @https://dl.antmicro.com/projects/renode/svd/ATSAME70Q21.svd
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