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This commit is contained in:
yangyanqing
2026-04-01 10:46:14 +08:00
parent d276237532
commit be1fc1495f
5 changed files with 1904 additions and 9 deletions
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18
UART_kx12A4.cs
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@@ -105,7 +105,8 @@ namespace Antmicro.Renode.Peripherals.CustomPeripherals
case (long)Registers.UCR_USR: //USR状态寄存器
value = (byte)(usr & 0xFF);
this.Log(LogLevel.Info, "Read USR: 0x{0:X2}", value);
// usr = (byte)(usr & (~USR_RBFI)); //usr寄存器，取消接收中断，与hw_uart_isr关联，暂定
usr = (byte)(usr & (~(USR_RBFI | USR_TCMP))); //usr寄存器，取消中断，与hw_uart_isr关联，暂定
UpdateInterrupts();
break;
case (long)Registers.MCR: //MCR调制控制寄存器
@@ -224,13 +225,14 @@ namespace Antmicro.Renode.Peripherals.CustomPeripherals
if (interrupt)
{
this.Log(LogLevel.Info, "Interrupt asserted");
machine.ScheduleAction(TimeInterval.FromMicroseconds(1),
_ => {
IRQ.Set(false);
this.Log(LogLevel.Info, "Interrupt deasserted");
});
}
machine.ScheduleAction(TimeInterval.FromMicroseconds(1),
_ => {
IRQ.Set(false);
this.Log(LogLevel.Info, "Interrupt deasserted");
});
}
@@ -397,7 +399,6 @@ namespace Antmicro.Renode.Peripherals.CustomPeripherals
}
}
// this.Wait(TimeInterval.FromMilliseconds(10)); 无法实现等待10ms，暂不实现
usr = (byte)(usr | USR_RBFI); //usr寄存器，置接收中断
UpdateInterrupts();
@@ -442,10 +443,9 @@ namespace Antmicro.Renode.Peripherals.CustomPeripherals
this.Log(LogLevel.Warning, "RX FIFO Already Full");
}
// this.Wait(TimeInterval.FromMilliseconds(10)); 无法实现等待10ms，暂不实现
usr = (byte)(usr | USR_RBFI); //usr寄存器，置接收中断
machine.ScheduleAction(TimeInterval.FromMicroseconds(10000),
_ => {
usr = (byte)(usr | USR_RBFI); //usr寄存器，置接收中断
UpdateInterrupts();
});