2026-04-17 08:55:34 +08:00
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//
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2026-05-25 15:33:24 +08:00
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// SJA1000 CAN 控制器外设实现(简化版,支持发送/接收队列,可配置长度)
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2026-04-17 08:55:34 +08:00
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// 仅支持 PeliCAN 模式的标准帧,不考虑 BasicCAN、扩展帧、错误处理、多帧、验收滤波和发送中断。
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// 寄存器地址映射基于 PeliCAN 模式,包含 MOD, CMR, SR, IR, IER, BTR0, BTR1, OCR, RXERR, TXERR,
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// 发送缓冲区(地址 16-26)、RBSA 和 CDR。命令寄存器位2=RRB,位3=CDO。
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// 所有寄存器可随时读写,无复位模式限制。
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//
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2026-05-25 15:33:24 +08:00
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// 队列长度可通过修改静态字段 MaxTxQueueSize 和 MaxRxQueueSize 调整。
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// 发送队列满时,CPU 发送请求被忽略,并设置 TBS=0(发送缓冲区忙);
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// 接收队列满时,外部注入的新帧被丢弃。
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//
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// 日志开关:EnableVerboseLog = false 可关闭所有日志输出。
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2026-04-17 08:55:34 +08:00
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//
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using System;
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using System.Text;
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using System.Collections.Generic;
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using Antmicro.Renode.Core;
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using Antmicro.Renode.Logging;
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using Antmicro.Renode.Peripherals.Bus;
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using Antmicro.Renode.Utilities;
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using Antmicro.Renode.Time;
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namespace Antmicro.Renode.Peripherals.CustomPeripherals
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{
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/// <summary>
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/// 简化版 SJA1000 CAN 控制器(PeliCAN 模式,仅标准帧)
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/// </summary>
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public class SJA1000_CAN : IDoubleWordPeripheral, IBytePeripheral, IKnownSize
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{
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2026-05-25 15:33:24 +08:00
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// 日志开关(设置为 false 可屏蔽所有日志)
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public static bool EnableVerboseLog = false;
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// 队列长度配置(可修改)
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public static int MaxTxQueueSize = 64; // 发送队列最大帧数
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public static int MaxRxQueueSize = 64; // 接收队列最大帧数
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2026-04-17 08:55:34 +08:00
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public SJA1000_CAN(IMachine machine)
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{
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this.machine = machine;
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IRQ = new GPIO();
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txBuffer = new byte[11];
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rxBuffer = new byte[11];
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2026-05-25 15:33:24 +08:00
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txFrameQueue = new Queue<byte[]>(); // 发送队列
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rxFrameQueue = new Queue<byte[]>(); // 接收队列
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2026-04-17 08:55:34 +08:00
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Reset();
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}
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public void Reset()
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{
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mod = 0;
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ier = 0;
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btr0 = 0;
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btr1 = 0;
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ocr = 0;
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rxerr = 0;
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txerr = 0;
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rbsa = 0;
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cdr = 0;
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sr_tbs = 1; // 发送缓冲区初始为空闲
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sr_rbs = 0; // 接收缓冲区初始为空
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ir = 0;
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Array.Clear(txBuffer, 0, txBuffer.Length);
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Array.Clear(rxBuffer, 0, rxBuffer.Length);
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2026-05-25 15:33:24 +08:00
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txFrameQueue.Clear();
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rxFrameQueue.Clear();
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2026-04-17 08:55:34 +08:00
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2026-05-25 15:33:24 +08:00
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lastInterruptState = false; // 重置中断边沿状态
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2026-04-17 08:55:34 +08:00
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UpdateInterrupts();
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2026-05-25 15:33:24 +08:00
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if (EnableVerboseLog)
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this.Log(LogLevel.Info, $"SJA1000 CAN controller reset (txQueueMax={MaxTxQueueSize}, rxQueueMax={MaxRxQueueSize})");
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2026-04-17 08:55:34 +08:00
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}
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// ================ IBusPeripheral 接口实现 ================
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public uint ReadDoubleWord(long offset)
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{
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return ReadByte(offset);
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}
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public void WriteDoubleWord(long offset, uint value)
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{
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WriteByte(offset, (byte)value);
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}
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public byte ReadByte(long offset)
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{
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byte value = 0;
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2026-05-25 15:33:24 +08:00
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lock (lockObject)
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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switch ((Registers)offset)
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{
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case Registers.MOD:
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value = mod;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read MOD: 0x{0:X2}", value);
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break;
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case Registers.CMR:
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read CMR (always 0)");
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value = 0;
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break;
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case Registers.SR:
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value = (byte)((sr_tbs << 2) | sr_rbs); // BS 恒为0
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read SR: TBS={0}, RBS={1} -> 0x{2:X2}", sr_tbs, sr_rbs, value);
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break;
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case Registers.IR:
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value = ir;
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ir = 0;
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UpdateIrFromRbs();
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// 中断被软件清除,重置边沿检测状态,允许下次条件满足时再次触发中断
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lastInterruptState = false;
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UpdateInterrupts();
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read IR: 0x{0:X2}, cleared", value);
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break;
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case Registers.IER:
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value = ier;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read IER: 0x{0:X2}", value);
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break;
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case Registers.BTR0:
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value = btr0;
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break;
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case Registers.BTR1:
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value = btr1;
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break;
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case Registers.OCR:
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value = ocr;
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break;
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case Registers.RXERR:
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value = rxerr;
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break;
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case Registers.TXERR:
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value = txerr;
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break;
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case Registers.RBSA:
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value = rbsa;
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break;
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case Registers.CDR:
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value = cdr;
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break;
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// 发送/接收缓冲区地址 16-26
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case Registers.TX_FRAME_INFO:
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case Registers.TX_ID1:
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case Registers.TX_ID2:
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case Registers.TX_DATA1:
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case Registers.TX_DATA2:
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case Registers.TX_DATA3:
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case Registers.TX_DATA4:
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case Registers.TX_DATA5:
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case Registers.TX_DATA6:
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case Registers.TX_DATA7:
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case Registers.TX_DATA8:
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int bufIndex = (int)(offset - (long)Registers.TX_FRAME_INFO) / 4;
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if (sr_rbs == 1)
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{
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value = rxBuffer[bufIndex];
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read RX buffer[{0}]: 0x{1:X2}", bufIndex, value);
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}
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else
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{
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value = txBuffer[bufIndex];
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read TX buffer[{0}]: 0x{1:X2}", bufIndex, value);
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}
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break;
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2026-04-17 08:55:34 +08:00
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2026-05-25 15:33:24 +08:00
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default:
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Read from unimplemented offset 0x{0:X}", offset);
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value = 0;
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break;
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}
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2026-04-17 08:55:34 +08:00
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}
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return value;
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}
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public void WriteByte(long offset, byte value)
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{
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2026-05-25 15:33:24 +08:00
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lock (lockObject)
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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switch ((Registers)offset)
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{
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case Registers.MOD:
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mod = value;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Write MOD: 0x{0:X2}", value);
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break;
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case Registers.CMR:
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Write CMR: 0x{0:X2}", value);
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if ((value & CMR_TR) != 0)
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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// 发送请求
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if (sr_tbs == 1)
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{
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var frame = new byte[11];
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if (txFrameQueue.Count < (MaxTxQueueSize - 1))
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{
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Array.Copy(txBuffer, frame, 11);
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txFrameQueue.Enqueue(frame);
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Array.Clear(txBuffer, 0, txBuffer.Length);
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sr_tbs = 1;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Frame enqueued for transmission, queue size: {0}", txFrameQueue.Count);
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}
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else if (txFrameQueue.Count == (MaxTxQueueSize - 1))
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{
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Array.Copy(txBuffer, frame, 11);
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txFrameQueue.Enqueue(frame);
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Array.Clear(txBuffer, 0, txBuffer.Length);
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sr_tbs = 0;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Frame enqueued, TX queue now full, TBS cleared");
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}
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else
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{
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sr_tbs = 0;
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if (EnableVerboseLog) this.Log(LogLevel.Warning, "Send request while TBS=0 ignored");
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}
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}
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else
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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if (EnableVerboseLog) this.Log(LogLevel.Warning, "Send request while TBS=0 ignored");
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2026-04-17 08:55:34 +08:00
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}
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}
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2026-05-25 15:33:24 +08:00
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if ((value & CMR_RRB) != 0)
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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LoadNextRxFrame();
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Receive buffer released");
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2026-04-17 08:55:34 +08:00
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}
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2026-05-25 15:33:24 +08:00
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if ((value & CMR_CDO) != 0)
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2026-04-17 08:55:34 +08:00
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{
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2026-05-25 15:33:24 +08:00
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// 清除数据溢出(无操作,但保留接口)
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Clear data overflow (no effect)");
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2026-04-17 08:55:34 +08:00
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}
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2026-05-25 15:33:24 +08:00
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break;
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case Registers.SR:
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if (EnableVerboseLog) this.Log(LogLevel.Warning, "Attempted write to read-only SR");
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break;
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case Registers.IR:
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if (EnableVerboseLog) this.Log(LogLevel.Warning, "Attempted write to read-only IR");
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break;
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case Registers.IER:
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ier = (byte)(value & 0x01);
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UpdateIrFromRbs();
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UpdateInterrupts();
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Write IER: 0x{0:X2}", ier);
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break;
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case Registers.BTR0:
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btr0 = value;
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if (EnableVerboseLog) this.Log(LogLevel.Info, "Write BTR0: 0x{0:X2}", value);
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break;
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case Registers.BTR1:
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btr1 = value;
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|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write BTR1: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case Registers.OCR:
|
|
|
|
|
|
ocr = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write OCR: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case Registers.RXERR:
|
|
|
|
|
|
rxerr = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write RXERR: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case Registers.TXERR:
|
|
|
|
|
|
txerr = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write TXERR: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case Registers.RBSA:
|
|
|
|
|
|
rbsa = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write RBSA: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case Registers.CDR:
|
|
|
|
|
|
cdr = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write CDR: 0x{0:X2}", value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
// 发送缓冲区写入
|
|
|
|
|
|
case Registers.TX_FRAME_INFO:
|
|
|
|
|
|
case Registers.TX_ID1:
|
|
|
|
|
|
case Registers.TX_ID2:
|
|
|
|
|
|
case Registers.TX_DATA1:
|
|
|
|
|
|
case Registers.TX_DATA2:
|
|
|
|
|
|
case Registers.TX_DATA3:
|
|
|
|
|
|
case Registers.TX_DATA4:
|
|
|
|
|
|
case Registers.TX_DATA5:
|
|
|
|
|
|
case Registers.TX_DATA6:
|
|
|
|
|
|
case Registers.TX_DATA7:
|
|
|
|
|
|
case Registers.TX_DATA8:
|
|
|
|
|
|
int bufIndex = (int)(offset - (long)Registers.TX_FRAME_INFO) / 4;
|
|
|
|
|
|
if (sr_tbs == 1)
|
|
|
|
|
|
{
|
|
|
|
|
|
txBuffer[bufIndex] = value;
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write TX buffer[{0}]: 0x{1:X2}", bufIndex, value);
|
|
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Warning, "Write to TX buffer while TBS=0 ignored");
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
default:
|
|
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Write to unimplemented offset 0x{0:X} = 0x{1:X2}", offset, value);
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
// ================ 内部辅助方法 ================
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
|
|
|
|
|
private void UpdateIrFromRbs()
|
|
|
|
|
|
{
|
|
|
|
|
|
if (sr_rbs == 1)
|
|
|
|
|
|
ir |= IR_RI;
|
|
|
|
|
|
else
|
2026-05-25 15:33:24 +08:00
|
|
|
|
ir = (byte)(ir & ~IR_RI);
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
private void UpdateInterrupts()
|
|
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
bool currentInterrupt = ((ir & IR_RI) != 0) && ((ier & IER_RIE) != 0);
|
|
|
|
|
|
if (currentInterrupt && !lastInterruptState)
|
2026-04-17 08:55:34 +08:00
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
IRQ.Set(true);
|
2026-04-17 08:55:34 +08:00
|
|
|
|
machine.ScheduleAction(TimeInterval.FromMicroseconds(1), _ =>
|
|
|
|
|
|
{
|
|
|
|
|
|
IRQ.Set(false);
|
|
|
|
|
|
});
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) this.Log(LogLevel.Info, "Interrupt pulse generated (RI)");
|
|
|
|
|
|
}
|
|
|
|
|
|
lastInterruptState = currentInterrupt;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
2026-05-25 15:33:24 +08:00
|
|
|
|
|
|
|
|
|
|
private readonly object lockObject = new object();
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
|
|
|
|
|
/// <summary>
|
|
|
|
|
|
/// 获取发送队列中所有帧的字符串表示(每帧以空格分隔的十六进制字节,帧间用换行分隔)
|
2026-05-25 15:33:24 +08:00
|
|
|
|
/// 调用后清空发送队列,并恢复发送缓冲区状态(如果之前因队列满被锁定)。
|
2026-04-17 08:55:34 +08:00
|
|
|
|
/// </summary>
|
|
|
|
|
|
public string GetTxBufferDataString()
|
|
|
|
|
|
{
|
|
|
|
|
|
lock (lockObject)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (txFrameQueue.Count == 0)
|
|
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine("GetTxBufferDataString: no frames in TX queue");
|
|
|
|
|
|
if (sr_tbs == 0) sr_tbs = 1;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
return null;
|
|
|
|
|
|
}
|
|
|
|
|
|
var sb = new StringBuilder();
|
|
|
|
|
|
while (txFrameQueue.Count > 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
var frame = txFrameQueue.Dequeue();
|
|
|
|
|
|
for (int i = 0; i < frame.Length; i++)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (i > 0) sb.Append(" ");
|
|
|
|
|
|
sb.Append(frame[i].ToString("X2"));
|
|
|
|
|
|
}
|
2026-05-25 15:33:24 +08:00
|
|
|
|
sb.AppendLine();
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
string result = sb.ToString().TrimEnd();
|
2026-05-25 15:33:24 +08:00
|
|
|
|
sr_tbs = 1;
|
|
|
|
|
|
if (EnableVerboseLog) Console.WriteLine("GetTxBufferDataString returning: " + result);
|
2026-04-17 08:55:34 +08:00
|
|
|
|
return result;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
2026-05-25 15:33:24 +08:00
|
|
|
|
|
2026-04-17 08:55:34 +08:00
|
|
|
|
/// <summary>
|
|
|
|
|
|
/// 外部接口注入一帧接收数据(11字节的十六进制字符串,空格分隔)
|
|
|
|
|
|
/// 可多次调用以注入多帧,帧将存入接收队列。
|
2026-05-25 15:33:24 +08:00
|
|
|
|
/// 若接收队列已满,则新帧被丢弃。
|
2026-04-17 08:55:34 +08:00
|
|
|
|
/// </summary>
|
|
|
|
|
|
public void SendRxBufferDataString(string frameString)
|
|
|
|
|
|
{
|
|
|
|
|
|
lock (lockObject)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (string.IsNullOrWhiteSpace(frameString))
|
|
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine("SendRxBufferDataString: empty string, ignored");
|
2026-04-17 08:55:34 +08:00
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
string[] parts = frameString.Split(new[] { ' ', '\t' }, StringSplitOptions.RemoveEmptyEntries);
|
|
|
|
|
|
if (parts.Length != 11)
|
|
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine($"SendRxBufferDataString: expected 11 bytes, got {parts.Length}, ignored");
|
2026-04-17 08:55:34 +08:00
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
byte[] frame = new byte[11];
|
|
|
|
|
|
for (int i = 0; i < 11; i++)
|
|
|
|
|
|
{
|
|
|
|
|
|
string part = parts[i].Trim();
|
|
|
|
|
|
if (!byte.TryParse(part, System.Globalization.NumberStyles.HexNumber,
|
|
|
|
|
|
System.Globalization.CultureInfo.InvariantCulture, out byte b))
|
|
|
|
|
|
{
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine($"SendRxBufferDataString: invalid hex byte '{part}' at index {i}, set to 0");
|
2026-04-17 08:55:34 +08:00
|
|
|
|
b = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
frame[i] = b;
|
|
|
|
|
|
}
|
2026-05-25 15:33:24 +08:00
|
|
|
|
|
|
|
|
|
|
if (rxFrameQueue.Count >= MaxRxQueueSize)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (EnableVerboseLog) Console.WriteLine($"SendRxBufferDataString: RX queue full (max={MaxRxQueueSize}), frame dropped");
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-04-17 08:55:34 +08:00
|
|
|
|
rxFrameQueue.Enqueue(frame);
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine($"Frame enqueued to RX queue, size: {rxFrameQueue.Count}");
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
|
|
|
|
|
if (sr_rbs == 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
LoadNextRxFrame();
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
private void LoadNextRxFrame()
|
|
|
|
|
|
{
|
|
|
|
|
|
if (rxFrameQueue.Count > 0)
|
|
|
|
|
|
{
|
|
|
|
|
|
var frame = rxFrameQueue.Dequeue();
|
|
|
|
|
|
Array.Copy(frame, rxBuffer, 11);
|
|
|
|
|
|
sr_rbs = 1;
|
|
|
|
|
|
UpdateIrFromRbs();
|
|
|
|
|
|
UpdateInterrupts();
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine("Loaded next RX frame into buffer, queue remaining: {0}", rxFrameQueue.Count);
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
else
|
|
|
|
|
|
{
|
|
|
|
|
|
sr_rbs = 0;
|
|
|
|
|
|
UpdateIrFromRbs();
|
|
|
|
|
|
UpdateInterrupts();
|
2026-05-25 15:33:24 +08:00
|
|
|
|
if (EnableVerboseLog) Console.WriteLine("RX queue empty, buffer cleared");
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// ================ 属性 ================
|
|
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
public long Size => 0x80;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
|
|
|
|
|
public GPIO IRQ { get; }
|
|
|
|
|
|
|
|
|
|
|
|
// ================ 寄存器枚举 ================
|
|
|
|
|
|
|
|
|
|
|
|
private enum Registers : long
|
|
|
|
|
|
{
|
|
|
|
|
|
MOD = 0x00,
|
|
|
|
|
|
CMR = 0x04,
|
2026-05-25 15:33:24 +08:00
|
|
|
|
SR = 0x08,
|
|
|
|
|
|
IR = 0x0C,
|
2026-04-17 08:55:34 +08:00
|
|
|
|
IER = 0x10,
|
|
|
|
|
|
BTR0 = 0x18,
|
|
|
|
|
|
BTR1 = 0x1C,
|
2026-05-25 15:33:24 +08:00
|
|
|
|
OCR = 0x20,
|
|
|
|
|
|
RXERR = 0x38,
|
|
|
|
|
|
TXERR = 0x3C,
|
|
|
|
|
|
TX_FRAME_INFO = 0x40,
|
2026-04-17 08:55:34 +08:00
|
|
|
|
TX_ID1 = 0x44,
|
|
|
|
|
|
TX_ID2 = 0x48,
|
|
|
|
|
|
TX_DATA1 = 0x4C,
|
|
|
|
|
|
TX_DATA2 = 0x50,
|
|
|
|
|
|
TX_DATA3 = 0x54,
|
|
|
|
|
|
TX_DATA4 = 0x58,
|
|
|
|
|
|
TX_DATA5 = 0x5C,
|
|
|
|
|
|
TX_DATA6 = 0x60,
|
|
|
|
|
|
TX_DATA7 = 0x64,
|
2026-05-25 15:33:24 +08:00
|
|
|
|
TX_DATA8 = 0x68,
|
|
|
|
|
|
RBSA = 0x78,
|
|
|
|
|
|
CDR = 0x7C,
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// ================ 常量位定义 ================
|
|
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private const byte CMR_TR = 0x01;
|
|
|
|
|
|
private const byte CMR_RRB = 0x04;
|
|
|
|
|
|
private const byte CMR_CDO = 0x08;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private const byte SR_BS = 0x80;
|
|
|
|
|
|
private const byte SR_TBS = 0x04;
|
|
|
|
|
|
private const byte SR_RBS = 0x01;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private const byte IR_RI = 0x01;
|
|
|
|
|
|
private const byte IER_RIE = 0x01;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
|
|
|
|
|
// ================ 私有字段 ================
|
|
|
|
|
|
|
|
|
|
|
|
private readonly IMachine machine;
|
|
|
|
|
|
|
|
|
|
|
|
private byte mod;
|
|
|
|
|
|
private byte ier;
|
|
|
|
|
|
private byte btr0, btr1;
|
|
|
|
|
|
private byte ocr;
|
|
|
|
|
|
private byte rxerr, txerr;
|
|
|
|
|
|
private byte rbsa;
|
|
|
|
|
|
private byte cdr;
|
|
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private byte sr_tbs;
|
|
|
|
|
|
private byte sr_rbs;
|
|
|
|
|
|
private byte ir;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private bool lastInterruptState; // 用于中断边沿检测
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private readonly byte[] txBuffer;
|
|
|
|
|
|
private readonly byte[] rxBuffer;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
|
2026-05-25 15:33:24 +08:00
|
|
|
|
private readonly Queue<byte[]> txFrameQueue;
|
|
|
|
|
|
private readonly Queue<byte[]> rxFrameQueue;
|
2026-04-17 08:55:34 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|