leguoqing/FPGA_DESIGN_IP
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
b8fe9f77ec2478cf9ff31b2ade6b2d7dfad8b915
FPGA_DESIGN_IP/uart_cli_axil
History
eesimple b8fe9f77ec 首次提交
2026-03-06 16:22:17 +08:00
..
sim
首次提交
2026-03-06 16:22:17 +08:00
src
首次提交
2026-03-06 16:22:17 +08:00
axil_ram.v
首次提交
2026-03-06 16:22:17 +08:00
cmd_line_buffer.sv
首次提交
2026-03-06 16:22:17 +08:00