172 lines
4.8 KiB
Systemverilog
172 lines
4.8 KiB
Systemverilog
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module uart_rx (
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input logic clk_i,
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input logic rstn_i,
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input logic rx_i,
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input logic [15:0] cfg_div_i,
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input logic cfg_en_i,
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input logic cfg_parity_en_i,
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input logic cfg_even_parity_i,
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output logic busy_o,
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output logic parity_error_o,
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output logic overrun_o,
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input logic err_clr_i,
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output logic [7:0] rx_data_o,
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output logic rx_valid_o,
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input logic rx_ready_i
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);
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enum logic [2:0] {IDLE,START_BIT,DATA,PARITY,STOP_BIT} CS, NS;
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logic [7:0] reg_data;
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logic [2:0] reg_rx_sync;
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logic [2:0] reg_bit_count;
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logic parity_bit;
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logic [15:0] baud_cnt;
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logic baudgen_en;
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logic bit_done;
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logic start_bit;
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logic s_rx_fall;
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assign busy_o = (CS != IDLE);
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always_comb begin
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NS = CS;
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baudgen_en = 1'b0;
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start_bit = 1'b0;
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case(CS)
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IDLE: begin
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if (s_rx_fall) begin
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NS = START_BIT;
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baudgen_en = 1'b1;
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start_bit = 1'b1;
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end
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end
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START_BIT: begin
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baudgen_en = 1'b1;
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start_bit = 1'b1;
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if (bit_done)
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NS = DATA;
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end
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DATA: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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if (reg_bit_count == 3'h7) begin
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if (cfg_parity_en_i)
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NS = PARITY;
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else
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NS = STOP_BIT;
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end
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end
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end
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PARITY: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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NS = STOP_BIT;
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end
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end
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STOP_BIT: begin
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baudgen_en = 1'b1;
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if (bit_done) begin
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NS = IDLE;
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end
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end
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default:
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NS = IDLE;
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endcase
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end
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always_ff @(posedge clk_i or negedge rstn_i)
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begin
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if (rstn_i == 1'b0) begin
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CS <= IDLE;
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reg_data <= 8'hFF;
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reg_bit_count <= 'h0;
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parity_bit <= 1'b0;
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parity_error_o <= 1'b0;
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rx_valid_o <= 1'b0;
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overrun_o <= 1'b0;
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end else begin
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if(cfg_en_i)
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CS <= NS;
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else
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CS <= IDLE;
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rx_valid_o <= 0;
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case (CS)
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START_BIT:
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parity_bit <= ~cfg_even_parity_i;
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DATA:
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if (bit_done) begin
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parity_bit <= parity_bit ^ reg_rx_sync[2];
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reg_data <= {reg_rx_sync[2],reg_data[7:1]};
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if (reg_bit_count == 3'h7)
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reg_bit_count <= 'h0;
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else
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reg_bit_count <= reg_bit_count + 1;
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end
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PARITY:
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if (bit_done)
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if(parity_bit != reg_rx_sync[2])
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parity_error_o <= 1'b1;
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else
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parity_error_o <= 1'b0;
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STOP_BIT:
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if (bit_done) begin
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rx_valid_o <= 1'b1;
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overrun_o <= ~rx_ready_i;
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end
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endcase
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end
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end
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assign s_rx_fall = ~reg_rx_sync[1] & reg_rx_sync[2];
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always_ff @(posedge clk_i or negedge rstn_i) begin
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if (rstn_i == 1'b0)
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reg_rx_sync <= 3'b111;
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else begin
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if (cfg_en_i)
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reg_rx_sync <= {reg_rx_sync[1:0],rx_i};
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else
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reg_rx_sync <= 3'b111;
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end
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end
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always_ff @(posedge clk_i or negedge rstn_i) begin
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if (rstn_i == 1'b0) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b0;
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end else begin
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if(baudgen_en) begin
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if(!start_bit && (baud_cnt == cfg_div_i)) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b1;
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end else if(start_bit && (baud_cnt == {1'b0,cfg_div_i[15:1]})) begin
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baud_cnt <= 'h0;
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bit_done <= 1'b1;
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end else begin
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baud_cnt <= baud_cnt + 1;
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bit_done <= 1'b0;
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end
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end else begin
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baud_cnt <= 'h0;
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bit_done <= 1'b0;
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end
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end
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end
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assign rx_data_o = reg_data;
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endmodule |