30 lines
646 B
Systemverilog
30 lines
646 B
Systemverilog
module vip_clock
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#(
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parameter FREQUENCY_MHZ = 1,
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parameter PHASE_DEGREE = 0
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)
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(
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input int duty_percent = 50,//dynamical parameter
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input int jitter_percent = 0,//dynamical parameter
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output clk
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);
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logic ideal_clk;
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initial begin
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ideal_clk = 0;
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#(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
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forever begin
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ideal_clk = 0;
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#(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);
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ideal_clk = 1;
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#(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
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end
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end
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assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk = ideal_clk;
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endmodule
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