49 lines
2.3 KiB
Systemverilog
49 lines
2.3 KiB
Systemverilog
/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*add all port here*/
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/*use "logic" to replace "logic" and "logic" ports*/
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/*use "wire" to replace "inout" ports*/
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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parameter STREAM_WIDTH = 8;
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parameter BUF_SIZE = 4096; // in bytes
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parameter SEG_SIZE = 256; // in bytes
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logic clk;
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logic rst_n;
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logic enable;
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logic [7:0] max_resp_time; // ms
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logic [31:0] buf_status;
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logic [31:0] counter_rx_beats;
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logic [31:0] counter_rx_bursts;
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logic [31:0] counter_rx_segments;
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logic [STREAM_WIDTH-1:0] tdata;
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logic tvalid;
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logic tlast;
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logic [STREAM_WIDTH/8-1:0] tkeep;
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logic [STREAM_WIDTH/8-1:0] tstrb;
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logic tready;
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logic buf_clk;
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logic [$clog2(BUF_SIZE)-1:0] buf_addr;
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logic [STREAM_WIDTH/8-1:0] buf_wea;
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logic [STREAM_WIDTH-1:0] buf_wdata;
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logic [STREAM_WIDTH-1:0] buf_rdata;
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logic list_clk;
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logic [11:0] list_addr;
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logic [ 3:0] list_wea;
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logic [31:0] list_wdata;
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logic [31:0] list_rdata;
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*initialize all "logic" ports here
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/*all inputs default as 0;modify if necessary
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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/*do not modify
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*/
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`TOP_ENTITY `TOP_INSTANCE(.*);
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