57 lines
1.7 KiB
Tcl
57 lines
1.7 KiB
Tcl
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#TODO:set the top module name with extention
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set TOP_FILE stream_rx_if.sv
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#TODO:set the top entity architecuture,vhdl file only;If the top module file is verilog,just ignore this var
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set TOP_VHD_ARCH Behavioral
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#TODO:set the coverage collect option
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set COVERAGE_OPTION sbfce
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#TODO:set the root path of simlation library,relative to the run.tcl
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set SIM_LIB_ROOT ../../../../../../03_simlib
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#set SIM_LIB_ROOT d:/02_work/simlib
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#TODO:sset the simulator excutable path
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set SIM_TOOL_PATH c:/questasim64_10.7
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#TODO: device family, microsemi/actel only
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set ACTEL_FAMILY proasic3l
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#TODO:set simulator name
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set SIMULATOR questasim
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#TODO:set simulator verion
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set SIMULATOR_VER 10.7
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#TODO:set simulator platform
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set SIMULATOR_PLATFORM nt64
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#TODO:set fpga par tools
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set FPGA_KIT_VER libero11.8
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#TODO:set vhdl library full path
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#set VHDL_LIB $SIM_LIB_ROOT/vhdl/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
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#TODO:set verilog library full pth
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#set VLOG_LIB $SIM_LIB_ROOT/verilog/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
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file mkdir coverage
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file mkdir wave
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file mkdir data
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file mkdir work
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#DO NOT MODIFYset the coverage data dirctory,relative to the run.tcl
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set COVERAGE_OUTPUT_DIR ../coverage
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#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
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set WAVE_OUTPUT_DIR ../wave
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#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
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set WORK_LIB_DIR ../work
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#DO NOT MODIFYget the top most module name
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set TOP_ENTITY [file rootname ${TOP_FILE}]
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#DO NOT MODIFYget the top most module language,vhdl or verilog
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set TOP_FILE_LANG [file extension ${TOP_FILE}]
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#DO NOT MODIFYse the top most instance name,with "u0_" prefix
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set TOP_INSTANCE u0_${TOP_ENTITY}
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