Logo
Explore Help
Register Sign In
leguoqing/FPGA_DESIGN_IP
1
0
Fork 0
You've already forked FPGA_DESIGN_IP
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
b8fe9f77ec2478cf9ff31b2ade6b2d7dfad8b915
FPGA_DESIGN_IP/ssp_1/src
History
eesimple b8fe9f77ec 首次提交
2026-03-06 16:22:17 +08:00
..
ssp_combo_channel_1_axi_bram_ctrl_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_axi_datamover_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_axil_reg_if_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_axil_reg_if_1_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_axis_data_fifo_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_axis_data_fifo_1_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_blk_mem_gen_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_regfile_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_regfile_1_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_ssp_rx_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_ssp_tx_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_stream_rx_ctrl_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_stream_tx_ctrl_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_xlslice_0_0
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1_ooc.xdc
首次提交
2026-03-06 16:22:17 +08:00
ssp_combo_channel_1.v
首次提交
2026-03-06 16:22:17 +08:00
Powered by Gitea Version: 1.25.4 Page: 13ms Template: 6ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API