139 lines
4.7 KiB
Systemverilog
139 lines
4.7 KiB
Systemverilog
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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module io_generic_fifo
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#(
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parameter DATA_WIDTH = 32,
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parameter BUFFER_DEPTH = 2,
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parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH)
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)
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(
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input logic clk_i,
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input logic rstn_i,
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input logic clr_i,
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output logic [LOG_BUFFER_DEPTH:0] elements_o,
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output logic [DATA_WIDTH-1 : 0] data_o,
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output logic valid_o,
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input logic ready_i,
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input logic valid_i,
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input logic [DATA_WIDTH-1 : 0] data_i,
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output logic ready_o
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);
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// Internal data structures
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/* verilator lint_off WIDTH */
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logic [LOG_BUFFER_DEPTH-1:0] pointer_in; // location to which we last wrote
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logic [LOG_BUFFER_DEPTH-1:0] pointer_out; // location from which we last sent
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/* lint_off */
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logic [LOG_BUFFER_DEPTH:0] elements; // number of elements in the buffer
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logic [DATA_WIDTH-1:0] buffer [BUFFER_DEPTH - 1 : 0];
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logic full;
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int unsigned loop1;
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assign full = (elements == BUFFER_DEPTH);
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assign elements_o = elements;
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always_ff @(posedge clk_i, negedge rstn_i)
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begin: elements_sequential
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if (rstn_i == 1'b0)
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elements <= 0;
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else
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begin
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if (clr_i)
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elements <= 0;
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else
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begin
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// ------------------
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// Are we filling up?
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// ------------------
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// One out, none in
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if (ready_i && valid_o && (!valid_i || full))
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elements <= elements - 1;
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// None out, one in
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else if ((!valid_o || !ready_i) && valid_i && !full)
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elements <= elements + 1;
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// Else, either one out and one in, or none out and none in - stays unchanged
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end
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end
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end
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always_ff @(posedge clk_i, negedge rstn_i)
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begin: buffers_sequential
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if (rstn_i == 1'b0)
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begin
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for (loop1 = 0 ; loop1 < BUFFER_DEPTH ; loop1 = loop1 + 1)
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buffer[loop1] <= 0;
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end
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else
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begin
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// Update the memory
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if (valid_i && !full)
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buffer[pointer_in] <= data_i;
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end
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end
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always_ff @(posedge clk_i, negedge rstn_i)
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begin: sequential
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if (rstn_i == 1'b0)
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begin
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pointer_out <= 0;
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pointer_in <= 0;
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end
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else
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begin
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if(clr_i)
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begin
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pointer_out <= 0;
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pointer_in <= 0;
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end
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else
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begin
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// ------------------------------------
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// Check what to do with the input side
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// ------------------------------------
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// We have some input, increase by 1 the input pointer
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if (valid_i && !full)
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begin
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if (pointer_in == $unsigned(BUFFER_DEPTH - 1))
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pointer_in <= 0;
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else
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pointer_in <= pointer_in + 1;
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end
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// Else we don't have any input, the input pointer stays the same
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// -------------------------------------
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// Check what to do with the output side
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// -------------------------------------
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// We had pushed one flit out, we can try to go for the next one
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if (ready_i && valid_o)
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begin
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if (pointer_out == $unsigned(BUFFER_DEPTH - 1))
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pointer_out <= 0;
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else
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pointer_out <= pointer_out + 1;
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end
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// Else stay on the same output location
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end
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end
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end
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// Update output ports
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assign data_o = buffer[pointer_out];
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assign valid_o = (elements != 0);
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assign ready_o = ~full;
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endmodule |