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2026-03-06 16:22:17 +08:00

85 lines
2.2 KiB
Systemverilog

`timescale 1ns/1ps
module
`CASE_NAME();
`include "../instantiate_top.sv"
final mti_fli::mti_Cmd("do ../saveucdb.tcl");
/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
/*to end the simulation commandary*/
/*if you want to end the simulation case by case,just comment the line
/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
//TODO:
// instance vip
vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(aclk));
vip_uart #(.CAPTURE("raw")) u0_vip_uart(.rx(uart_tx), .tx(uart_rx));
axil_ram #(
.ADDR_WIDTH(12),
.DATA_WIDTH(32)
) u_axil_ram (
.clk (aclk),
.rst (~aresetn),
.s_axil_awvalid (m_axil_awvalid),
.s_axil_awready (m_axil_awready),
.s_axil_awaddr (m_axil_awaddr),
.s_axil_awprot (m_axil_awprot),
.s_axil_wvalid (m_axil_wvalid),
.s_axil_wready (m_axil_wready),
.s_axil_wdata (m_axil_wdata),
.s_axil_wstrb (m_axil_wstrb),
.s_axil_bvalid (m_axil_bvalid),
.s_axil_bready (m_axil_bready),
.s_axil_bresp (m_axil_bresp),
.s_axil_arvalid (m_axil_arvalid),
.s_axil_arready (m_axil_arready),
.s_axil_araddr (m_axil_araddr),
.s_axil_arprot (m_axil_arprot),
.s_axil_rvalid (m_axil_rvalid),
.s_axil_rready (m_axil_rready),
.s_axil_rdata (m_axil_rdata),
.s_axil_rresp (m_axil_rresp)
);
initial begin
aresetn = 0;
#1us aresetn = 1;
end
task send_cmd(input string cmd);
begin
foreach(cmd[i]) begin
u0_vip_uart.send(cmd[i]);
end
end
endtask
initial begin
#1ns;
@(posedge aresetn);
#1ms;
send_cmd("\n");
#5ms;
send_cmd("r 0 -t\n");
#20ms;
send_cmd("\x03");
#5ms;
send_cmd("r 0 -t\n");
#20ms;
send_cmd("r\n");
#20ms;
send_cmd("\x03");
#5ms;
end
endmodule