75 lines
3.2 KiB
Systemverilog
75 lines
3.2 KiB
Systemverilog
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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module uart
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#(
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parameter integer CLOCK_FREQUENCY = 50e6,
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parameter integer BAUD_RATE = 115200,
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parameter logic CFG_PARITY_EN = 1'b0, // 0: disable parity; 1: enable parity
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parameter logic CFG_EVEN_PARITY = 1'b0, // 0: odd parity; 1: even parity
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parameter logic CFG_STOP_BIT = 1'b0 // 0: 1 stop bit; 1: 2 stop bit
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)
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(
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input logic clk,
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input logic rstn,
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input logic rx_i, // Receiver input
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output logic tx_o, // Transmitter output
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output logic rx_valid,
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output logic [7:0] rx_data,
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input logic rx_ready,
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input logic tx_valid,
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input logic [7:0] tx_data,
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output logic tx_ready
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);
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// register addresses
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// TODO: check that stop bits are really not necessary here
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uart_rx uart_rx_i
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(
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.clk_i ( clk ),
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.rstn_i ( rstn ),
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.rx_i ( rx_i ),
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.cfg_en_i ( 1'b1 ),
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.cfg_div_i ( CLOCK_FREQUENCY/BAUD_RATE ),
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.cfg_parity_en_i ( CFG_PARITY_EN ),
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.cfg_even_parity_i ( CFG_EVEN_PARITY ),
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.busy_o ( ),
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.parity_error_o ( ),
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.overrun_o ( ),
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.err_clr_i ( 1'b1 ),
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.rx_data_o ( rx_data ),
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.rx_valid_o ( rx_valid ),
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.rx_ready_i ( rx_ready )
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);
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uart_tx uart_tx_i
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(
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.clk_i ( clk ),
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.rstn_i ( rstn ),
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.tx_o ( tx_o ),
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.busy_o ( ),
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.cfg_en_i ( 1'b1 ),
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.cfg_div_i ( CLOCK_FREQUENCY/BAUD_RATE ),
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.cfg_parity_en_i ( CFG_PARITY_EN ),
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.cfg_even_parity_i ( CFG_EVEN_PARITY ),
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.cfg_stop_bits_i ( CFG_STOP_BIT ),
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.tx_data_i ( tx_data ),
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.tx_valid_i ( tx_valid ),
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.tx_ready_o ( tx_ready )
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);
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endmodule
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