390 lines
16 KiB
Plaintext
390 lines
16 KiB
Plaintext
# Reading C:/questasim64_10.7/tcl/vsim/pref.tcl
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# // Questa Sim-64
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# // Version 10.7 win64 Dec 7 2017
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# //
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# // Copyright 1991-2017 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // QuestaSim and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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# sstc.preference
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# invalid command name "sstc.preference"
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do runone.tcl -n 1 -t 10ms
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# on
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# stream_rx_if.sv
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# Behavioral
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# sbfce
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# ../../../../../../03_simlib
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# c:/questasim64_10.7
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# proasic3l
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# questasim
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# 10.7
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# nt64
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# libero11.8
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# ../coverage
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# ../wave
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# ../work
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# stream_rx_if
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# .sv
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# u0_stream_rx_if
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim
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# ---->parsing the command line....argc=4,args=-n 1 -t 10ms*************************
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# case number=001
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# simulation time=10ms
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# ---->parsing the command line complete ***************************
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# func001
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# func001
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# ---->check if override the run.tcl commandary...............
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# reading modelsim.ini
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# on
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# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap std c:/questasim64_10.7/std
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# Modifying modelsim.ini
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap ieee c:/questasim64_10.7/ieee
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# Modifying modelsim.ini
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# ../../../01_source/01_func
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# ../../../01_source/02_timing
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# false
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# false
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# CASE_NAME func001
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# CASE_NAME func001 TOP_ENTITY stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {}
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms
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# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms
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# ** Warning: (vlib-34) Library already exists at "../work/func001".
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap work ../work/func001
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# Modifying modelsim.ini
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# 0
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# 0
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# ../file_ver.f
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# ../file_vhd.f
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# glbl
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# ---->compile verilog source files ,testbench and models using ../file_ver.f........
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# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
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# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# ** Error: ../../src/stream_rx_if.sv(114): (vlib-2730) Undefined variable: 'tx_state_next'.
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# ** Error: c:/questasim64_10.7/win64/vlog failed.
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# Error in macro ./run.tcl line 224
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# c:/questasim64_10.7/win64/vlog failed.
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# while executing
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# "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003"
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# invoked from within
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# "if {$SIM_TYPE == "timing"} {
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#
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# set SDF_TYPE "-sdfmax";
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# set SDFCOM_TYPE "-maxdelays";
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#
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# puts "*************************timing simulat..."
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do runone.tcl -n 1 -t 10ms
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# reading modelsim.ini
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# on
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# stream_rx_if.sv
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# Behavioral
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# sbfce
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# ../../../../../../03_simlib
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# c:/questasim64_10.7
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# proasic3l
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# questasim
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# 10.7
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# nt64
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# libero11.8
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# ../coverage
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# ../wave
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# ../work
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# stream_rx_if
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# .sv
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# u0_stream_rx_if
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim
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# ---->parsing the command line....argc=4,args=-n 1 -t 10ms*************************
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# case number=001
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# simulation time=10ms
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# ---->parsing the command line complete ***************************
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# func001
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# func001
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# ---->check if override the run.tcl commandary...............
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# reading modelsim.ini
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# on
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# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap std c:/questasim64_10.7/std
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# Modifying modelsim.ini
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap ieee c:/questasim64_10.7/ieee
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# Modifying modelsim.ini
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# ../../../01_source/01_func
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# ../../../01_source/02_timing
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# false
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# false
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# CASE_NAME func001
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# CASE_NAME func001 TOP_ENTITY stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {}
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms
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# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms
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# ** Warning: (vlib-34) Library already exists at "../work/func001".
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap work ../work/func001
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# Modifying modelsim.ini
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# 0
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# 0
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# ../file_ver.f
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# ../file_vhd.f
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# glbl
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# ---->compile verilog source files ,testbench and models using ../file_ver.f........
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# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
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# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# ** Error: ../../src/stream_rx_if.sv(75): (vlib-13003) Enum member 'RX_INTERVAL' has value that is outside the representable range of the enum.
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# ** Error: c:/questasim64_10.7/win64/vlog failed.
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# Error in macro ./run.tcl line 224
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# c:/questasim64_10.7/win64/vlog failed.
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# while executing
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# "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003"
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# invoked from within
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# "if {$SIM_TYPE == "timing"} {
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#
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# set SDF_TYPE "-sdfmax";
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# set SDFCOM_TYPE "-maxdelays";
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#
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# puts "*************************timing simulat..."
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do runone.tcl -n 1 -t 10ms
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# reading modelsim.ini
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# on
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# stream_rx_if.sv
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# Behavioral
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# sbfce
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# ../../../../../../03_simlib
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# c:/questasim64_10.7
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# proasic3l
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# questasim
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# 10.7
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# nt64
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# libero11.8
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# ../coverage
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# ../wave
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# ../work
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# stream_rx_if
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# .sv
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# u0_stream_rx_if
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim
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# ---->parsing the command line....argc=4,args=-n 1 -t 10ms*************************
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# case number=001
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# simulation time=10ms
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# ---->parsing the command line complete ***************************
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# func001
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# func001
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# ---->check if override the run.tcl commandary...............
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# reading modelsim.ini
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# on
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# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap std c:/questasim64_10.7/std
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# Modifying modelsim.ini
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap ieee c:/questasim64_10.7/ieee
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# Modifying modelsim.ini
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# ../../../01_source/01_func
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# ../../../01_source/02_timing
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# false
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# false
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# CASE_NAME func001
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# CASE_NAME func001 TOP_ENTITY stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {}
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms
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# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms
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# ** Warning: (vlib-34) Library already exists at "../work/func001".
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap work ../work/func001
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# Modifying modelsim.ini
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# 0
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# 0
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# ../file_ver.f
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# ../file_vhd.f
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# glbl
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# ---->compile verilog source files ,testbench and models using ../file_ver.f........
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# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
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# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf
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# Start time: 17:39:37 on Nov 21,2025
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# ** Note: (vsim-3812) Design is being optimized...
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# ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'buf_clk'.
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# ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'buf_rdata'.
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# ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'list_clk'.
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# Optimization failed
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# Error loading design
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# Error: Error loading design
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# Pausing macro execution
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# MACRO ./run.tcl PAUSED at line 224
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do runone.tcl -n 1 -t 10ms
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# End time: 17:43:27 on Nov 21,2025, Elapsed time: 0:03:50
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# Errors: 3, Warnings: 0
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# reading modelsim.ini
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# on
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# stream_rx_if.sv
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# Behavioral
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# sbfce
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# ../../../../../../03_simlib
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# c:/questasim64_10.7
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# proasic3l
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# questasim
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# 10.7
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# nt64
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# libero11.8
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# ../coverage
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# ../wave
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# ../work
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# stream_rx_if
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# .sv
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# u0_stream_rx_if
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim
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# ---->parsing the command line....argc=4,args=-n 1 -t 10ms*************************
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# case number=001
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# simulation time=10ms
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# ---->parsing the command line complete ***************************
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# func001
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# func001
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# ---->check if override the run.tcl commandary...............
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# reading modelsim.ini
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# on
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# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap std c:/questasim64_10.7/std
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# Modifying modelsim.ini
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap ieee c:/questasim64_10.7/ieee
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# Modifying modelsim.ini
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# ../../../01_source/01_func
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# ../../../01_source/02_timing
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# false
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# false
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# CASE_NAME func001
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# CASE_NAME func001 TOP_ENTITY stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {}
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms
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# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms
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# ** Warning: (vlib-34) Library already exists at "../work/func001".
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap work ../work/func001
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# Modifying modelsim.ini
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# 0
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# 0
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# ../file_ver.f
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# ../file_vhd.f
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# glbl
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# ---->compile verilog source files ,testbench and models using ../file_ver.f........
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# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
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# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# ** Error: (vlib-13069) ../../src/stream_rx_if.sv(41): near "localparam": syntax error, unexpected localparam, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.
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# ** Error: ../../src/stream_rx_if.sv(62): (vlib-2730) Undefined variable: 'ADDR_STEP'.
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# ** Error: ../../src/stream_rx_if.sv(114): (vlib-2730) Undefined variable: 'SEG_TOTAL'.
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# ** Error: ../../src/stream_rx_if.sv(180): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'.
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# ** Error: ../../src/stream_rx_if.sv(190): (vlib-2730) Undefined variable: 'SEG_TOTAL'.
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# ** Error: ../../src/stream_rx_if.sv(200): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'.
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# ** Error: ../../src/stream_rx_if.sv(200): (vlib-2730) Undefined variable: 'SEG_TOTAL'.
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# ** Error: ../../src/stream_rx_if.sv(226): (vlib-2730) Undefined variable: 'SEG_TOTAL'.
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# ** Error: ../../src/stream_rx_if.sv(254): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'.
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# ** Error: ../../src/stream_rx_if.sv(267): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'.
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# ** Error: ../../src/stream_rx_if.sv(283): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'.
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# ** Error: c:/questasim64_10.7/win64/vlog failed.
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# Error in macro ./run.tcl line 224
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# c:/questasim64_10.7/win64/vlog failed.
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# while executing
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# "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003"
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# invoked from within
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# "if {$SIM_TYPE == "timing"} {
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#
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# set SDF_TYPE "-sdfmax";
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# set SDFCOM_TYPE "-maxdelays";
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#
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# puts "*************************timing simulat..."
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do runone.tcl -n 1 -t 10ms
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# reading modelsim.ini
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# on
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# stream_rx_if.sv
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# Behavioral
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# sbfce
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# ../../../../../../03_simlib
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# c:/questasim64_10.7
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# proasic3l
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# questasim
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# 10.7
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# nt64
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# libero11.8
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# ../coverage
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# ../wave
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# ../work
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# stream_rx_if
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# .sv
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# u0_stream_rx_if
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim
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# ---->parsing the command line....argc=4,args=-n 1 -t 10ms*************************
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# case number=001
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# simulation time=10ms
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# ---->parsing the command line complete ***************************
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# func001
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# func001
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# ---->check if override the run.tcl commandary...............
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# reading modelsim.ini
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# on
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# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap std c:/questasim64_10.7/std
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# Modifying modelsim.ini
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap ieee c:/questasim64_10.7/ieee
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# Modifying modelsim.ini
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# ../../../01_source/01_func
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# ../../../01_source/02_timing
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# false
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# false
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# CASE_NAME func001
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# CASE_NAME func001 TOP_ENTITY stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {}
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# CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms
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# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms
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# ** Warning: (vlib-34) Library already exists at "../work/func001".
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# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
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# vmap work ../work/func001
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# Modifying modelsim.ini
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# 0
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# 0
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# ../file_ver.f
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# ../file_vhd.f
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# glbl
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# ---->compile verilog source files ,testbench and models using ../file_ver.f........
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# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
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# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf
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# Start time: 17:44:11 on Nov 21,2025
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# ** Note: (vsim-3812) Design is being optimized...
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# ** Note: (vopt-143) Recognized 1 FSM in module "stream_rx_if(fast)".
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# ** Warning: tb.sv(7): (vopt-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
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# ---->checing the simulator status to decide whether to restore the wave session..................
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# ---->the runstatus is :ready
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# ---->trying restore to saved wave window..................
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# 0
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001
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# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001++++++++++++++++++++++++++++++++
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# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001
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# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001++++++++++++++++++++++++++++++++
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add wave -position insertpoint sim:/func001/u0_stream_rx_if/*
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# End time: 17:45:00 on Nov 21,2025, Elapsed time: 0:00:49
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# Errors: 0, Warnings: 1
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