113 lines
2.9 KiB
Systemverilog
113 lines
2.9 KiB
Systemverilog
`timescale 1ns/1ps
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module
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`CASE_NAME();
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`include "../instantiate_top.sv"
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final mti_fli::mti_Cmd("do ../saveucdb.tcl");
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*to end the simulation commandary*/
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/*if you want to end the simulation case by case,just comment the line
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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// instance vip
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vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
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initial begin
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enable = 1'b1;
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max_resp_time = 8'h1;
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tvalid = 0;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 0;
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rst_n = 0;
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#1us rst_n = 1;
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end
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task send_stream(input int number_of_beats, input int beat_cycle = 8, input logic last_beat_valid = 1);
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begin
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repeat(number_of_beats-last_beat_valid) begin
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@(posedge clk);
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tvalid = 1'b1;
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tdata = $urandom;
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tkeep = 1'b1;
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tstrb = 1'b1;
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tlast = 1'b0;
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repeat(beat_cycle-1) begin
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@(posedge clk);
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tvalid = 0;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 0;
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end
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end
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if (last_beat_valid) begin
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@(posedge clk);
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tvalid = 1'b1;
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tdata = $urandom;
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tkeep = 1'b1;
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tstrb = 1'b1;
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tlast = 1'b1;
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repeat(beat_cycle-1) begin
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@(posedge clk);
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tvalid = 0;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 0;
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end
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end else begin
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@(posedge clk);
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tvalid = 1;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 1;
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repeat(beat_cycle-1) begin
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@(posedge clk);
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tvalid = 0;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 0;
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end
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end
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@(posedge clk);
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tvalid = 0;
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tdata = 0;
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tkeep = 0;
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tstrb = 0;
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tlast = 0;
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end
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endtask
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initial begin
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#1ns;
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@(posedge rst_n);
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#10us;
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send_stream(16);
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#50us;
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send_stream(20);
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#100us;
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send_stream(8);
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#1ms;
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send_stream(800);
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#10us;
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send_stream(300);
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end
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endmodule |