23 lines
356 B
Systemverilog
23 lines
356 B
Systemverilog
/*
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can bus physical model by leguoqing
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*/
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module can_transceiver
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(
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output logic rxd = 1,
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input logic txd,
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inout tri1 line
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);
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always@(*)
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if (line == 1'b0) rxd <= 1'b0;
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else rxd <= 1'b1;
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logic line_reg;
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always@(*)
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if (txd == 0) line_reg <= 0;
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else line_reg <= 1;
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assign line = line_reg ? 1'bz : 0;
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endmodule
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