34 lines
1.5 KiB
Systemverilog
34 lines
1.5 KiB
Systemverilog
/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*add all port here*/
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/*use "logic" to replace "logic" and "logic" ports*/
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/*use "wire" to replace "inout" ports*/
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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logic clk;
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logic aresetn;
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logic [7:0] tdata;
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logic tvalid;
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logic tready;
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logic ssp_clk;
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logic ssp_csn;
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logic ssp_data;
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logic ssp_tx_busy;
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*initialize all "logic" ports here
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/*all inputs default as 0,modify if necessary
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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/*do not modify
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*/
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`TOP_ENTITY `TOP_INSTANCE(.*);
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