73 lines
1.7 KiB
Systemverilog
73 lines
1.7 KiB
Systemverilog
`timescale 1ns/1ps
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module
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`CASE_NAME();
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`include "../instantiate_top.sv"
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final mti_fli::mti_Cmd("do ../saveucdb.tcl");
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initial begin
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$fsdbDumpfile("fsdb_wave.fsdb");
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$fsdbDumpvars;
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end
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*to end the simulation commandary*/
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/*if you want to end the simulation case by case,just comment the line
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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logic [7:0] ssp_rx_tdata;
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logic ssp_rx_tvalid;
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logic ssp_rx_tready = 0;
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logic [31:0] error_status;
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// instance vip
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vip_clock # (.FREQUENCY_MHZ(100)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
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vip_clock # (.FREQUENCY_MHZ(110)) u1_clock(.duty_percent(50), .jitter_percent(0), .clk(ssp_rx_clk));
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ssp_rx # (
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.FREQ_HZ(110e6),
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.SSP_HZ(10e6)
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) u_ssp_rx (
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.clk (ssp_rx_clk),
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.aresetn (aresetn),
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.tdata (ssp_rx_tdata),
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.tvalid (ssp_rx_tvalid),
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.tready (ssp_rx_tready),
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.ssp_clk (ssp_clk),
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.ssp_csn (ssp_csn),
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.ssp_data (ssp_data),
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.error_status (error_status)
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);
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initial begin
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aresetn = 1'b0;
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#200ns;
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aresetn = 1'b1;
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end
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initial begin
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tdata = 8'h00;
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tvalid = 1'b0;
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wait (!aresetn);
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#100ns;
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repeat (20) begin
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// send a byte
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tvalid = 1'b1;
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@(posedge tready) #1ns;
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tvalid = 1'b0;
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tdata++;
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end
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//$finish;
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end
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endmodule |