xilinx.com user stream_rx_if 1.0 interface_axis TDATA tdata TSTRB tstrb TKEEP tkeep TLAST tlast TVALID tvalid TREADY tready rst_n RST rst_n POLARITY ACTIVE_LOW buf_clk CLK buf_clk clk CLK clk ASSOCIATED_BUSIF interface_axis desc_clk CLK desc_clk buf_if buf_if buf_if DIN buf_wdata DOUT buf_rdata CLK buf_clk WE buf_wea ADDR buf_addr desc_if desc_if desc_if DIN desc_wdata DOUT desc_rdata CLK desc_clk WE desc_wea ADDR desc_addr xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis SystemVerilog stream_rx_if xilinx_anylanguagesynthesis_view_fileset viewChecksum a39eba53 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation SystemVerilog stream_rx_if xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a39eba53 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 7d5f69bb clk in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rst_n in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation max_resp_time in 7 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_status out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation counter_rx_beats out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation counter_rx_bursts out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation counter_rx_segments out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tdata in 7 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tvalid in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tlast in logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tkeep in 0 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 tstrb in 0 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 tready out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_clk out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_addr out 11 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_wea out 0 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_wdata out 7 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation buf_rdata in 7 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation desc_clk out logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation desc_addr out 11 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation desc_wea out 3 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation desc_wdata out 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation desc_rdata in 31 0 logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation FREQ_HZ Freq Hz 125000000 STREAM_WIDTH Stream Width 8 BUF_SIZE Buf Size 4096 SEG_SIZE Seg Size 256 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset wall_timer.sv systemVerilogSource stream_rx_if.sv systemVerilogSource CHECKSUM_4e3b52a1 xilinx_anylanguagebehavioralsimulation_view_fileset wall_timer.sv systemVerilogSource stream_rx_if.sv systemVerilogSource xilinx_xpgui_view_fileset xgui/stream_rx_if_v1_0.tcl tclSource CHECKSUM_7d5f69bb XGUI_VERSION_2 stream_rx_if_v1_0 FREQ_HZ Freq Hz 125000000 STREAM_WIDTH Stream Width 8 BUF_SIZE Buf Size 4096 SEG_SIZE Seg Size 256 Component_Name stream_rx_if_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /UserIP stream_rx_if_v1_0 package_project XPM_CDC XPM_FIFO XPM_MEMORY 2 2025-11-23T11:42:29Z 2023.2