xilinx.com user ssp_combo_channel_1 1.0 M_AXI_MM2S ARADDR M_AXI_MM2S_araddr 31 0 ARBURST M_AXI_MM2S_arburst 1 0 ARCACHE M_AXI_MM2S_arcache 3 0 ARID M_AXI_MM2S_arid 3 0 ARLEN M_AXI_MM2S_arlen 7 0 ARPROT M_AXI_MM2S_arprot 2 0 ARREADY M_AXI_MM2S_arready ARSIZE M_AXI_MM2S_arsize 2 0 ARUSER M_AXI_MM2S_aruser 3 0 ARVALID M_AXI_MM2S_arvalid RDATA M_AXI_MM2S_rdata 127 0 RLAST M_AXI_MM2S_rlast RREADY M_AXI_MM2S_rready RRESP M_AXI_MM2S_rresp 1 0 RVALID M_AXI_MM2S_rvalid DATA_WIDTH 128 PROTOCOL AXI4 FREQ_HZ 100000000 ID_WIDTH 4 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 4 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_ONLY HAS_BURST 0 HAS_LOCK 0 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 0 HAS_REGION 0 HAS_WSTRB 0 HAS_BRESP 0 HAS_RRESP 1 SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 2 NUM_WRITE_OUTSTANDING 2 MAX_BURST_LENGTH 16 PHASE 0 NUM_READ_THREADS 1 NUM_WRITE_THREADS 1 RUSER_BITS_PER_BYTE 0 WUSER_BITS_PER_BYTE 0 M_AXI_S2MM AWADDR M_AXI_S2MM_awaddr 31 0 AWBURST M_AXI_S2MM_awburst 1 0 AWCACHE M_AXI_S2MM_awcache 3 0 AWID M_AXI_S2MM_awid 3 0 AWLEN M_AXI_S2MM_awlen 7 0 AWPROT M_AXI_S2MM_awprot 2 0 AWREADY M_AXI_S2MM_awready AWSIZE M_AXI_S2MM_awsize 2 0 AWUSER M_AXI_S2MM_awuser 3 0 AWVALID M_AXI_S2MM_awvalid BREADY M_AXI_S2MM_bready BRESP M_AXI_S2MM_bresp 1 0 BVALID M_AXI_S2MM_bvalid WDATA M_AXI_S2MM_wdata 127 0 WLAST M_AXI_S2MM_wlast WREADY M_AXI_S2MM_wready WSTRB M_AXI_S2MM_wstrb 15 0 WVALID M_AXI_S2MM_wvalid DATA_WIDTH 128 PROTOCOL AXI4 FREQ_HZ 100000000 ID_WIDTH 4 ADDR_WIDTH 32 AWUSER_WIDTH 4 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE WRITE_ONLY HAS_BURST 1 HAS_LOCK 0 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 0 HAS_REGION 0 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 0 SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 2 NUM_WRITE_OUTSTANDING 2 MAX_BURST_LENGTH 16 PHASE 0 NUM_READ_THREADS 1 NUM_WRITE_THREADS 1 RUSER_BITS_PER_BYTE 0 WUSER_BITS_PER_BYTE 0 S_AXI_TXDESC ARADDR S_AXI_TXDESC_araddr 14 0 ARBURST S_AXI_TXDESC_arburst 1 0 ARCACHE S_AXI_TXDESC_arcache 3 0 ARLEN S_AXI_TXDESC_arlen 7 0 ARLOCK S_AXI_TXDESC_arlock ARPROT S_AXI_TXDESC_arprot 2 0 ARREADY S_AXI_TXDESC_arready ARSIZE S_AXI_TXDESC_arsize 2 0 ARVALID S_AXI_TXDESC_arvalid AWADDR S_AXI_TXDESC_awaddr 14 0 AWBURST S_AXI_TXDESC_awburst 1 0 AWCACHE S_AXI_TXDESC_awcache 3 0 AWLEN S_AXI_TXDESC_awlen 7 0 AWLOCK S_AXI_TXDESC_awlock AWPROT S_AXI_TXDESC_awprot 2 0 AWREADY S_AXI_TXDESC_awready AWSIZE S_AXI_TXDESC_awsize 2 0 AWVALID S_AXI_TXDESC_awvalid BREADY S_AXI_TXDESC_bready BRESP S_AXI_TXDESC_bresp 1 0 BVALID S_AXI_TXDESC_bvalid RDATA S_AXI_TXDESC_rdata 63 0 RLAST S_AXI_TXDESC_rlast RREADY S_AXI_TXDESC_rready RRESP S_AXI_TXDESC_rresp 1 0 RVALID S_AXI_TXDESC_rvalid WDATA S_AXI_TXDESC_wdata 63 0 WLAST S_AXI_TXDESC_wlast WREADY S_AXI_TXDESC_wready WSTRB S_AXI_TXDESC_wstrb 7 0 WVALID S_AXI_TXDESC_wvalid DATA_WIDTH 64 PROTOCOL AXI4 FREQ_HZ 100000000 ID_WIDTH 0 ADDR_WIDTH 15 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 1 HAS_LOCK 1 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 0 HAS_REGION 0 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 1 NUM_READ_OUTSTANDING 2 NUM_WRITE_OUTSTANDING 2 MAX_BURST_LENGTH 256 PHASE 0 NUM_READ_THREADS 1 NUM_WRITE_THREADS 1 RUSER_BITS_PER_BYTE 0 WUSER_BITS_PER_BYTE 0 s_axil_rx AWADDR s_axil_rx_awaddr 31 0 AWPROT s_axil_rx_awprot 2 0 AWVALID s_axil_rx_awvalid AWREADY s_axil_rx_awready WDATA s_axil_rx_wdata 31 0 WSTRB s_axil_rx_wstrb 3 0 WVALID s_axil_rx_wvalid WREADY s_axil_rx_wready BRESP s_axil_rx_bresp 1 0 BVALID s_axil_rx_bvalid BREADY s_axil_rx_bready ARADDR s_axil_rx_araddr 31 0 ARPROT s_axil_rx_arprot 2 0 ARVALID s_axil_rx_arvalid ARREADY s_axil_rx_arready RDATA s_axil_rx_rdata 31 0 RRESP s_axil_rx_rresp 1 0 RVALID s_axil_rx_rvalid RREADY s_axil_rx_rready DATA_WIDTH 32 PROTOCOL AXI4LITE FREQ_HZ 100000000 ID_WIDTH 0 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 0 HAS_LOCK 0 HAS_PROT 1 HAS_CACHE 0 HAS_QOS 0 HAS_REGION 0 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 1 NUM_WRITE_OUTSTANDING 1 MAX_BURST_LENGTH 1 PHASE 0 NUM_READ_THREADS 1 NUM_WRITE_THREADS 1 RUSER_BITS_PER_BYTE 0 WUSER_BITS_PER_BYTE 0 s_axil_tx AWADDR s_axil_tx_awaddr 31 0 AWPROT s_axil_tx_awprot 2 0 AWVALID s_axil_tx_awvalid AWREADY s_axil_tx_awready WDATA s_axil_tx_wdata 31 0 WSTRB s_axil_tx_wstrb 3 0 WVALID s_axil_tx_wvalid WREADY s_axil_tx_wready BRESP s_axil_tx_bresp 1 0 BVALID s_axil_tx_bvalid BREADY s_axil_tx_bready ARADDR s_axil_tx_araddr 31 0 ARPROT s_axil_tx_arprot 2 0 ARVALID s_axil_tx_arvalid ARREADY s_axil_tx_arready RDATA s_axil_tx_rdata 31 0 RRESP s_axil_tx_rresp 1 0 RVALID s_axil_tx_rvalid RREADY s_axil_tx_rready DATA_WIDTH 32 PROTOCOL AXI4LITE FREQ_HZ 100000000 ID_WIDTH 0 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 0 HAS_LOCK 0 HAS_PROT 1 HAS_CACHE 0 HAS_QOS 0 HAS_REGION 0 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 1 NUM_WRITE_OUTSTANDING 1 MAX_BURST_LENGTH 1 PHASE 0 NUM_READ_THREADS 1 NUM_WRITE_THREADS 1 RUSER_BITS_PER_BYTE 0 WUSER_BITS_PER_BYTE 0 RST.ARESETN RST aresetn POLARITY ACTIVE_LOW CLK.CLK CLK clk FREQ_HZ 100000000 FREQ_TOLERANCE_HZ 0 PHASE 0 ASSOCIATED_BUSIF M_AXI_MM2S:M_AXI_S2MM:S_AXI_TXDESC:s_axil_rx:s_axil_tx ASSOCIATED_RESET aresetn M_AXI_MM2S 0x100000000 32 M_AXI_S2MM 0x100000000 32 s_axil_rx {SEG_axil_reg_if_0_reg0;/axil_reg_if_0/s_axil/reg0;0x0000;256;xilinx.com:user:axil_reg_if:1.0;register;/axil_reg_if_0;s_axil;NONE;NONE} Reg0 /axil_reg_if_0:reg0 0x0000 0x00000100 32 register s_axil_tx {SEG_axil_reg_if_1_reg0;/axil_reg_if_1/s_axil/reg0;0x0000;256;xilinx.com:user:axil_reg_if:1.0;register;/axil_reg_if_1;s_axil;NONE;NONE} Reg0 /axil_reg_if_1:reg0 0x0000 0x00000100 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog ssp_combo_channel_1 xilinx_anylanguagesynthesis_xilinx_com_ip_axi_bram_ctrl_4_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axi_datamover_5_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_axil_reg_if_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_regfile_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_ssp_rx_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_ssp_tx_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_stream_rx_ctrl_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_stream_tx_ctrl_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum e6546327 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog ssp_combo_channel_1 xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_bram_ctrl_4_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axi_datamover_5_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axil_reg_if_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_regfile_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_ssp_rx_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_ssp_tx_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_stream_rx_ctrl_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_stream_tx_ctrl_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum fed56c3b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f64a5dae M_AXI_MM2S_araddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arid out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_aruser out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_rdata in 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_MM2S_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awaddr out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awid out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awlen out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awuser out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_wdata out 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_wstrb out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_AXI_S2MM_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_araddr in 14 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arburst in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arcache in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arlen in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arlock in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arsize in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awaddr in 14 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awburst in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awcache in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awlen in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awlock in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awsize in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_rdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_rlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_wdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_wlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_wstrb in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_TXDESC_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_rx_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axil_tx_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_rx_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_rx_csn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_rx_data in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_tx_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_tx_csn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ssp_tx_data out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset src/ssp_combo_channel_1_axi_bram_ctrl_0_0/ssp_combo_channel_1_axi_bram_ctrl_0_0.xci xci IMPORTED_FILE CELL_NAME_axi_bram_ctrl_0 src/ssp_combo_channel_1_axi_datamover_0_0/ssp_combo_channel_1_axi_datamover_0_0.xci xci IMPORTED_FILE CELL_NAME_axi_datamover_0 src/ssp_combo_channel_1_axil_reg_if_0_0/ssp_combo_channel_1_axil_reg_if_0_0.xci xci IMPORTED_FILE CELL_NAME_axil_reg_if_0 src/ssp_combo_channel_1_axil_reg_if_1_0/ssp_combo_channel_1_axil_reg_if_1_0.xci xci IMPORTED_FILE CELL_NAME_axil_reg_if_1 src/ssp_combo_channel_1_axis_data_fifo_0_0/ssp_combo_channel_1_axis_data_fifo_0_0.xci xci IMPORTED_FILE CELL_NAME_axis_data_fifo_0 src/ssp_combo_channel_1_axis_data_fifo_1_0/ssp_combo_channel_1_axis_data_fifo_1_0.xci xci IMPORTED_FILE CELL_NAME_axis_data_fifo_1 src/ssp_combo_channel_1_blk_mem_gen_0_0/ssp_combo_channel_1_blk_mem_gen_0_0.xci xci IMPORTED_FILE CELL_NAME_blk_mem_gen_0 src/ssp_combo_channel_1_regfile_0_0/ssp_combo_channel_1_regfile_0_0.xci xci IMPORTED_FILE CELL_NAME_regfile_0 src/ssp_combo_channel_1_regfile_1_0/ssp_combo_channel_1_regfile_1_0.xci xci IMPORTED_FILE CELL_NAME_regfile_1 src/ssp_combo_channel_1_ssp_rx_0_0/ssp_combo_channel_1_ssp_rx_0_0.xci xci IMPORTED_FILE CELL_NAME_ssp_rx_0 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