module vip_clock
    #(
    parameter FREQUENCY_MHZ = 1,
    parameter PHASE_DEGREE = 0
    )
    (
    input int duty_percent = 50,//dynamical parameter
    input int jitter_percent = 0,//dynamical parameter
    output clk
    );



logic ideal_clk;

initial begin
    ideal_clk = 0;
    #(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
    forever begin
        ideal_clk = 0;
        #(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);

        ideal_clk = 1;
        #(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
    end
end

assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk =  ideal_clk;
endmodule