#quit -sim
#ATTTION : MODIFY THIS FILE AS YOU WANT
#ATTTION : MODIFY THIS FILE AS YOU WANT
#ATTTION : MODIFY THIS FILE AS YOU WANT
#ATTTION : MODIFY THIS FILE AS YOU WANT
#ATTTION : MODIFY THIS FILE AS YOU WANT
#unbound the the "work" lib dir from vsim,to remove it

#when error do not save wave list
if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
    source savewave.tcl
}
#catch {q -sim} res
#dataset close -all

echo on
.main clear

puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"

vmap std $SIM_TOOL_PATH/std  ;
vmap ieee $SIM_TOOL_PATH/ieee   ;

set FUNC_SOURCE_DIR   ../../../01_source/01_func
set TIMING_SOURCE_DIR ../../../01_source/02_timing

set source_vhdl false
set source_verilog false

set LIB_OPTION ""
set LOG_OPTION ""

#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
#    #-----------actel----------
#    #puts "IDE IS $FPGA_KIT_VER!"
#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
#		set LOG_OPTION "-vhdlvariablelogging"
#    }
#    if {[string equal -nocase vhd $TOP_FILE_LANG]} {
#        vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
#    } else {
#        vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
#    }
#    set LIB_OPTION "-L ${ACTEL_FAMILY}"
#
#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
#    #puts "IDE IS $FPGA_KIT_VER!"
#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
#        set source_vhdl true
#		set LOG_OPTION "-vhdlvariablelogging"
#    }
#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
#        set source_verilog true
#    }
#    if { [string equal -nocase true $source_vhdl] } {
#        #-----------xilinx vhdl----------
#        #puts "vhdl file exist!"
#        vmap simprim       $VHDL_LIB/simprim
#        vmap unisim        $VHDL_LIB/unisim
#        vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
#        vmap unimacro      $VHDL_LIB/unimacro
#        set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
#    }
#
#    if { [string equal -nocase true $source_verilog] } {
#        #-----------xilinx verilog----------
#        #puts "verilog file exist!"
#        vmap unisims_ver       $VLOG_LIB/unisims_ver
#        vmap simprims_ver      $VLOG_LIB/simprims_ver
#        vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
#        vmap unimacro_ver      $VLOG_LIB/unimacro_ver
#        vmap secureip          $VLOG_LIB/secureip
#        set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
#    }
#}

set defs [dict create;] ;
dict append defs CASE_NAME $CASE_NAME;
dict append defs TOP_ENTITY $TOP_ENTITY;
dict append defs TOP_INSTANCE $TOP_INSTANCE;
dict append defs timing;
dict append defs SIM_TIME $SIM_TIME ;

set def_string "";
dict for {def_name def_value} $defs {
    set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
}
puts "the define string is:$def_string"


#file delete -force work            ;

vlib $WORK_LIB_DIR/${CASE_DIR};
vmap work $WORK_LIB_DIR/${CASE_DIR};
catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock        } res;
catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/     } res;

#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}

#if {[info exists 1]} {
#    set SIM_TIME $1
#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}



#by default,all cases use the same source file list
set VLOG_SOURCE_LIST ../file_ver.f;
set VHDL_SOURCE_LIST ../file_vhd.f;

#we specify individual file list for single case
if {[file exists file_ver.f ]} {
    puts "---->using case dependent verilog file list"
    set VLOG_SOURCE_LIST file_ver.f;
}

if {[file exists file_vhd.f ]} {
    puts "---->using case dependent vhdl file list"
    set VHDL_SOURCE_LIST file_vhd.f;
}

if {![string equal vhd $TOP_FILE_LANG]} {
    set GLBL glbl
}

if {$SIM_TYPE == "timing"} {

        set SDF_TYPE "-sdfmax";
        set SDFCOM_TYPE "-maxdelays";

    puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
        if {[string equal $CORNER_TYPE "01_min" ]} {
                set SDF_TYPE "-sdfmin";
                set SDFCOM_TYPE "-mindelays";
                puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
        } elseif {[string equal $CORNER_TYPE "02_type" ]} {
                set SDF_TYPE "-sdftyp";
                set SDFCOM_TYPE "-typdelays";
                puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
        } elseif {[string equal $CORNER_TYPE "03_max" ]} {
                set SDF_TYPE "-sdfmax";
                set SDFCOM_TYPE "-maxdelays";
                puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
        }
        
        if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
                puts "++++++++++ develop kit is libero ++++++++++";
        } else {
                puts "++++++++++ develop kit is not libero ++++++++++";
                set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
        }
        
        sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom

        #in timing simulation ,here only glbl may be compiled seperately
    if {[file exists  ${VLOG_SOURCE_LIST}]} {
        vlog  -incr -quiet  -sv  +cover=${COVERAGE_OPTION}  +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
    }

    vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v

    vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string

    eval vopt  ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
        +initmem+0 +initreg+0 +initwire+0;


    eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout  \
    +no_notifier +no_tchk_msg\
    work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
        ${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;

    do ../suppresswarning.tcl


    catch {run ${SIM_TIME} } res
} else {


#compile source files
    if {[file exists ${VLOG_SOURCE_LIST}]} {
        puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
#       vlog -incr -quiet   +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
        vlog  -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
    }


    if {[file exists ${VHDL_SOURCE_LIST}]} {
        puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
        vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
    }

#        eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
#        +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
#            +initmem+0 +initreg+0 +initwire+0 \
#            -suppress 2912 \
#            -suppress 1127

    #to mask 211 error
    catch {
                if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
                                eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
                                        -t 1ps -wlfopt -wlfcompress -nostdout  \
                                        +initmem+0 +initreg+0 +initwire+0 \
                                        +no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
                                        -classdebug \
                                        glbl work.${CASE_NAME} \
                                        -wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
                } else {
                        restart -f
                }
        } res;

    do ../suppresswarning.tcl

    catch {do wave.tcl} res

    set TEMP_REF_FILES info.txt;
    write report -l $TEMP_REF_FILES

    catch {run ${SIM_TIME} } res

    do ../saveucdb.tcl
#}

set current_path [pwd]
puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"