#TODO:set the top module name with extention
set TOP_FILE stream_tx_if.sv

#TODO:set the top entity architecuture,vhdl file only;If the top module file is verilog,just ignore this var
set TOP_VHD_ARCH Behavioral

#TODO:set the coverage collect option
set COVERAGE_OPTION sbfce

#TODO:set the root path of simlation library,relative to the run.tcl
set SIM_LIB_ROOT  ../../../../../../03_simlib
#set SIM_LIB_ROOT d:/02_work/simlib

#TODO:sset the simulator excutable path
set SIM_TOOL_PATH c:/questasim64_10.7

#TODO: device family, microsemi/actel only
set ACTEL_FAMILY proasic3l

#TODO:set simulator name
set SIMULATOR questasim
#TODO:set simulator verion
set SIMULATOR_VER 10.7
#TODO:set simulator platform
set SIMULATOR_PLATFORM nt64
#TODO:set fpga par tools
set FPGA_KIT_VER libero11.8
#TODO:set vhdl library full path
#set VHDL_LIB $SIM_LIB_ROOT/vhdl/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
#TODO:set verilog library full pth
#set VLOG_LIB $SIM_LIB_ROOT/verilog/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER


file mkdir coverage
file mkdir wave
file mkdir data
file mkdir work

#DO NOT MODIFYset the coverage data dirctory,relative to the run.tcl
set COVERAGE_OUTPUT_DIR ../coverage
#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
set WAVE_OUTPUT_DIR ../wave
#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
set WORK_LIB_DIR ../work
#DO NOT MODIFYget the top most module name
set TOP_ENTITY [file rootname ${TOP_FILE}]
#DO NOT MODIFYget the top most module language,vhdl or verilog
set TOP_FILE_LANG [file extension  ${TOP_FILE}]
#DO NOT MODIFYse the top most instance name,with "u0_" prefix
set TOP_INSTANCE u0_${TOP_ENTITY}