# Reading C:/questasim64_10.7/tcl/vsim/pref.tcl # // Questa Sim-64 # // Version 10.7 win64 Dec 7 2017 # // # // Copyright 1991-2017 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # sstc.preference # invalid command name "sstc.preference" do runone.tcl -n 1 -t 10ms # on # stream_rx_if.sv # Behavioral # sbfce # ../../../../../../03_simlib # c:/questasim64_10.7 # proasic3l # questasim # 10.7 # nt64 # libero11.8 # ../coverage # ../wave # ../work # stream_rx_if # .sv # u0_stream_rx_if # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim # ---->parsing the command line....argc=4,args=-n 1 -t 10ms************************* # case number=001 # simulation time=10ms # ---->parsing the command line complete *************************** # func001 # func001 # ---->check if override the run.tcl commandary............... # reading modelsim.ini # on # +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++ # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap std c:/questasim64_10.7/std # Modifying modelsim.ini # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap ieee c:/questasim64_10.7/ieee # Modifying modelsim.ini # ../../../01_source/01_func # ../../../01_source/02_timing # false # false # CASE_NAME func001 # CASE_NAME func001 TOP_ENTITY stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms # the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms # ** Warning: (vlib-34) Library already exists at "../work/func001". # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap work ../work/func001 # Modifying modelsim.ini # 0 # 0 # ../file_ver.f # ../file_vhd.f # glbl # ---->compile verilog source files ,testbench and models using ../file_ver.f........ # ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch. # ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # ** Error: ../../src/stream_rx_if.sv(114): (vlib-2730) Undefined variable: 'tx_state_next'. # ** Error: c:/questasim64_10.7/win64/vlog failed. # Error in macro ./run.tcl line 224 # c:/questasim64_10.7/win64/vlog failed. # while executing # "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003" # invoked from within # "if {$SIM_TYPE == "timing"} { # # set SDF_TYPE "-sdfmax"; # set SDFCOM_TYPE "-maxdelays"; # # puts "*************************timing simulat..." do runone.tcl -n 1 -t 10ms # reading modelsim.ini # on # stream_rx_if.sv # Behavioral # sbfce # ../../../../../../03_simlib # c:/questasim64_10.7 # proasic3l # questasim # 10.7 # nt64 # libero11.8 # ../coverage # ../wave # ../work # stream_rx_if # .sv # u0_stream_rx_if # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim # ---->parsing the command line....argc=4,args=-n 1 -t 10ms************************* # case number=001 # simulation time=10ms # ---->parsing the command line complete *************************** # func001 # func001 # ---->check if override the run.tcl commandary............... # reading modelsim.ini # on # +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++ # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap std c:/questasim64_10.7/std # Modifying modelsim.ini # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap ieee c:/questasim64_10.7/ieee # Modifying modelsim.ini # ../../../01_source/01_func # ../../../01_source/02_timing # false # false # CASE_NAME func001 # CASE_NAME func001 TOP_ENTITY stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms # the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms # ** Warning: (vlib-34) Library already exists at "../work/func001". # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap work ../work/func001 # Modifying modelsim.ini # 0 # 0 # ../file_ver.f # ../file_vhd.f # glbl # ---->compile verilog source files ,testbench and models using ../file_ver.f........ # ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch. # ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # ** Error: ../../src/stream_rx_if.sv(75): (vlib-13003) Enum member 'RX_INTERVAL' has value that is outside the representable range of the enum. # ** Error: c:/questasim64_10.7/win64/vlog failed. # Error in macro ./run.tcl line 224 # c:/questasim64_10.7/win64/vlog failed. # while executing # "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003" # invoked from within # "if {$SIM_TYPE == "timing"} { # # set SDF_TYPE "-sdfmax"; # set SDFCOM_TYPE "-maxdelays"; # # puts "*************************timing simulat..." do runone.tcl -n 1 -t 10ms # reading modelsim.ini # on # stream_rx_if.sv # Behavioral # sbfce # ../../../../../../03_simlib # c:/questasim64_10.7 # proasic3l # questasim # 10.7 # nt64 # libero11.8 # ../coverage # ../wave # ../work # stream_rx_if # .sv # u0_stream_rx_if # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim # ---->parsing the command line....argc=4,args=-n 1 -t 10ms************************* # case number=001 # simulation time=10ms # ---->parsing the command line complete *************************** # func001 # func001 # ---->check if override the run.tcl commandary............... # reading modelsim.ini # on # +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++ # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap std c:/questasim64_10.7/std # Modifying modelsim.ini # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap ieee c:/questasim64_10.7/ieee # Modifying modelsim.ini # ../../../01_source/01_func # ../../../01_source/02_timing # false # false # CASE_NAME func001 # CASE_NAME func001 TOP_ENTITY stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms # the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms # ** Warning: (vlib-34) Library already exists at "../work/func001". # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap work ../work/func001 # Modifying modelsim.ini # 0 # 0 # ../file_ver.f # ../file_vhd.f # glbl # ---->compile verilog source files ,testbench and models using ../file_ver.f........ # ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch. # ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf # Start time: 17:39:37 on Nov 21,2025 # ** Note: (vsim-3812) Design is being optimized... # ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'buf_clk'. # ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'buf_rdata'. # ** Error (suppressible): ../instantiate_top.sv(49): (vopt-2247) The implicit port connection (.*) did not find a matching port, net, variable or interface instance for port 'list_clk'. # Optimization failed # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./run.tcl PAUSED at line 224 do runone.tcl -n 1 -t 10ms # End time: 17:43:27 on Nov 21,2025, Elapsed time: 0:03:50 # Errors: 3, Warnings: 0 # reading modelsim.ini # on # stream_rx_if.sv # Behavioral # sbfce # ../../../../../../03_simlib # c:/questasim64_10.7 # proasic3l # questasim # 10.7 # nt64 # libero11.8 # ../coverage # ../wave # ../work # stream_rx_if # .sv # u0_stream_rx_if # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim # ---->parsing the command line....argc=4,args=-n 1 -t 10ms************************* # case number=001 # simulation time=10ms # ---->parsing the command line complete *************************** # func001 # func001 # ---->check if override the run.tcl commandary............... # reading modelsim.ini # on # +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++ # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap std c:/questasim64_10.7/std # Modifying modelsim.ini # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap ieee c:/questasim64_10.7/ieee # Modifying modelsim.ini # ../../../01_source/01_func # ../../../01_source/02_timing # false # false # CASE_NAME func001 # CASE_NAME func001 TOP_ENTITY stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms # the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms # ** Warning: (vlib-34) Library already exists at "../work/func001". # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap work ../work/func001 # Modifying modelsim.ini # 0 # 0 # ../file_ver.f # ../file_vhd.f # glbl # ---->compile verilog source files ,testbench and models using ../file_ver.f........ # ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch. # ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # ** Error: (vlib-13069) ../../src/stream_rx_if.sv(41): near "localparam": syntax error, unexpected localparam, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER. # ** Error: ../../src/stream_rx_if.sv(62): (vlib-2730) Undefined variable: 'ADDR_STEP'. # ** Error: ../../src/stream_rx_if.sv(114): (vlib-2730) Undefined variable: 'SEG_TOTAL'. # ** Error: ../../src/stream_rx_if.sv(180): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'. # ** Error: ../../src/stream_rx_if.sv(190): (vlib-2730) Undefined variable: 'SEG_TOTAL'. # ** Error: ../../src/stream_rx_if.sv(200): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'. # ** Error: ../../src/stream_rx_if.sv(200): (vlib-2730) Undefined variable: 'SEG_TOTAL'. # ** Error: ../../src/stream_rx_if.sv(226): (vlib-2730) Undefined variable: 'SEG_TOTAL'. # ** Error: ../../src/stream_rx_if.sv(254): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'. # ** Error: ../../src/stream_rx_if.sv(267): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'. # ** Error: ../../src/stream_rx_if.sv(283): (vlib-2730) Undefined variable: 'SEG_ADDR_WIDTH'. # ** Error: c:/questasim64_10.7/win64/vlog failed. # Error in macro ./run.tcl line 224 # c:/questasim64_10.7/win64/vlog failed. # while executing # "vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003" # invoked from within # "if {$SIM_TYPE == "timing"} { # # set SDF_TYPE "-sdfmax"; # set SDFCOM_TYPE "-maxdelays"; # # puts "*************************timing simulat..." do runone.tcl -n 1 -t 10ms # reading modelsim.ini # on # stream_rx_if.sv # Behavioral # sbfce # ../../../../../../03_simlib # c:/questasim64_10.7 # proasic3l # questasim # 10.7 # nt64 # libero11.8 # ../coverage # ../wave # ../work # stream_rx_if # .sv # u0_stream_rx_if # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim # ---->parsing the command line....argc=4,args=-n 1 -t 10ms************************* # case number=001 # simulation time=10ms # ---->parsing the command line complete *************************** # func001 # func001 # ---->check if override the run.tcl commandary............... # reading modelsim.ini # on # +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++ # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap std c:/questasim64_10.7/std # Modifying modelsim.ini # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap ieee c:/questasim64_10.7/ieee # Modifying modelsim.ini # ../../../01_source/01_func # ../../../01_source/02_timing # false # false # CASE_NAME func001 # CASE_NAME func001 TOP_ENTITY stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} # CASE_NAME func001 TOP_ENTITY stream_rx_if TOP_INSTANCE u0_stream_rx_if timing {} SIM_TIME 10ms # the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=stream_rx_if+define+TOP_INSTANCE=u0_stream_rx_if+define+timing=+define+SIM_TIME=10ms # ** Warning: (vlib-34) Library already exists at "../work/func001". # QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap work ../work/func001 # Modifying modelsim.ini # 0 # 0 # ../file_ver.f # ../file_vhd.f # glbl # ---->compile verilog source files ,testbench and models using ../file_ver.f........ # ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch. # ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf # Start time: 17:44:11 on Nov 21,2025 # ** Note: (vsim-3812) Design is being optimized... # ** Note: (vopt-143) Recognized 1 FSM in module "stream_rx_if(fast)". # ** Warning: tb.sv(7): (vopt-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast. # ---->checing the simulator status to decide whether to restore the wave session.................. # ---->the runstatus is :ready # ---->trying restore to saved wave window.................. # 0 # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001 # +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001++++++++++++++++++++++++++++++++ # C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001 # +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/stream_rx_buffer/sim/func001++++++++++++++++++++++++++++++++ add wave -position insertpoint sim:/func001/u0_stream_rx_if/* # End time: 17:45:00 on Nov 21,2025, Elapsed time: 0:00:49 # Errors: 0, Warnings: 1