# Reading C:/questasim64_10.7/tcl/vsim/pref.tcl
# //  Questa Sim-64
# //  Version 10.7 win64 Dec  7 2017
# //
# //  Copyright 1991-2017 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# sstc.preference
# invalid command name "sstc.preference"
do runone.tcl -n 1 -t 20us
# on
# ssp_tx.sv
# Behavioral
# sbfce
# ../../../../../../03_simlib
# c:/questasim64_10.7
# proasic3l
# questasim
# 10.7
# nt64
# libero11.8
# ../coverage
# ../wave
# ../work
# ssp_tx
# .sv
# u0_ssp_tx
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim
# ---->parsing the command line....argc=4,args=-n 1 -t 20us*************************
# case number=001
# simulation time=20us
# ---->parsing the command line complete ***************************
# func001
# func001
# ---->check if override the run.tcl commandary...............
# reading modelsim.ini
# on
# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
# vmap std c:/questasim64_10.7/std 
# Modifying modelsim.ini
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
# vmap ieee c:/questasim64_10.7/ieee 
# Modifying modelsim.ini
# ../../../01_source/01_func
# ../../../01_source/02_timing
# false
# false
# CASE_NAME func001
# CASE_NAME func001 TOP_ENTITY ssp_tx
# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx
# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx timing {}
# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx timing {} SIM_TIME 20us
# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=ssp_tx+define+TOP_INSTANCE=u0_ssp_tx+define+timing=+define+SIM_TIME=20us
# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
# vmap work ../work/func001 
# Modifying modelsim.ini
# 0
# 0
# ../file_ver.f
# ../file_vhd.f
# glbl
# ---->compile verilog source files ,testbench and models using ../file_ver.f........
# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
# vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf 
# Start time: 14:35:39 on Oct 16,2025
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in module "ssp_tx(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "ssp_rx(fast)".
# ** Warning: tb.sv(7): (vopt-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
# ** Warning: func001.u_ssp_rx.genblk1: FREQ_HZ/SSP_HZ is not an even number, which means the SSP clock will be asymmetric!
#    Time: 0 ps  Scope: func001.u_ssp_rx.genblk1 File: ../../../ssp_rx/src/ssp_rx.sv Line: 30
# ** Warning: (vsim-PLI-3003) tb.sv(10): [TOFD] - System task or function '$fsdbDumpfile' is not defined.
#    Time: 0 ps  Iteration: 0  Instance: /func001 File: tb.sv
# ** Warning: (vsim-PLI-3003) tb.sv(11): [TOFD] - System task or function '$fsdbDumpvars' is not defined.
#    Time: 0 ps  Iteration: 0  Instance: /func001 File: tb.sv
# ---->checing the simulator status to decide whether to restore the wave session..................
# ---->the runstatus is :ready
# ---->trying  restore to saved wave window..................
# 0
# ** Error (suppressible): (vsim-12023) tb.sv(10): Cannot execute undefined system task/function '$fsdbDumpfile'
# ** Error (suppressible): (vsim-12023) tb.sv(11): Cannot execute undefined system task/function '$fsdbDumpvars'
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001
# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001++++++++++++++++++++++++++++++++
# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001
# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001++++++++++++++++++++++++++++++++
add wave -position insertpoint sim:/func001/u0_ssp_tx/*
add wave -position insertpoint sim:/func001/u_ssp_rx/*
# End time: 14:38:31 on Oct 16,2025, Elapsed time: 0:02:52
# Errors: 2, Warnings: 4