leguoqing/FPGA_DESIGN_IP
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eesimple
2026-03-06 16:22:17 +08:00
commit b8fe9f77ec
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uart_cli_axil/sim/mergeucdb.tcl Normal file
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#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
#ATTTION : DO NOT MODIFY THE WHOLE FILE
source globalset.tcl
if {[info exists TOP_FILE_LANG] && ![string compare ${TOP_FILE_LANG} ".vhd"]} {
vcover merge -stats=none -strip 0 -du [string tolower ${TOP_ENTITY}]([string tolower ${TOP_VHD_ARCH}]) -recursive -totals merge.ucdb ./coverage/*.ucdb
} else {
vcover merge -stats=none -strip 0 -du ${TOP_ENTITY} -recursive -totals merge.ucdb ./coverage/*.ucdb
}