首次提交

2026-03-06 16:22:17 +08:00
commit b8fe9f77ec
465 changed files with 115939 additions and 0 deletions
--- a/uart_cli_axil/sim/instantiate_top.sv
+++ b/uart_cli_axil/sim/instantiate_top.sv
@@ -0,0 +1,50 @@
+/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/ 
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*add all port here*/                                                            
+/*use "logic" to replace "logic" and "logic" ports*/                            
+/*use "wire" to replace "inout" ports*/                                          
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+//TODO:                                                                          	
+
+parameter ADDR_WIDTH = 12;
+parameter DATA_WIDTH = 32;
+
+logic aclk;
+logic aresetn;
+
+logic uart_rx;
+logic uart_tx;
+
+logic cmd_resetn;
+// axi lite master interface
+logic                    m_axil_awvalid;
+logic                    m_axil_awready;
+logic [ADDR_WIDTH-1:0]   m_axil_awaddr;
+logic [2:0]              m_axil_awprot;
+logic                    m_axil_wvalid;
+logic                    m_axil_wready;
+logic [DATA_WIDTH-1:0]   m_axil_wdata;
+logic [DATA_WIDTH/8-1:0] m_axil_wstrb;
+logic                    m_axil_bvalid;
+logic                    m_axil_bready;
+logic [1:0]              m_axil_bresp;
+logic                    m_axil_arvalid;
+logic                    m_axil_arready;
+logic [ADDR_WIDTH-1:0]   m_axil_araddr;
+logic [2:0]              m_axil_arprot;
+logic                    m_axil_rvalid;
+logic                    m_axil_rready;
+logic [DATA_WIDTH-1:0]   m_axil_rdata;
+logic [1:0]              m_axil_rresp;
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/   
+/*initialize all "logic" ports here                                                         
+/*all inputs default as 0;modify if necessary                                               
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/   
+//TODO:
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+                                                                                            
+/*do not modify
+*/
+`TOP_ENTITY #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) `TOP_INSTANCE(.*);