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85
uart_cli_axil/sim/func001/tb.sv
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85
uart_cli_axil/sim/func001/tb.sv
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`timescale 1ns/1ps
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module
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`CASE_NAME();
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`include "../instantiate_top.sv"
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final mti_fli::mti_Cmd("do ../saveucdb.tcl");
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/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
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/*to end the simulation commandary*/
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/*if you want to end the simulation case by case,just comment the line
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/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
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//TODO:
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// instance vip
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vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(aclk));
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vip_uart #(.CAPTURE("raw")) u0_vip_uart(.rx(uart_tx), .tx(uart_rx));
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axil_ram #(
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.ADDR_WIDTH(12),
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.DATA_WIDTH(32)
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) u_axil_ram (
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.clk (aclk),
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.rst (~aresetn),
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.s_axil_awvalid (m_axil_awvalid),
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.s_axil_awready (m_axil_awready),
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.s_axil_awaddr (m_axil_awaddr),
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.s_axil_awprot (m_axil_awprot),
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.s_axil_wvalid (m_axil_wvalid),
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.s_axil_wready (m_axil_wready),
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.s_axil_wdata (m_axil_wdata),
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.s_axil_wstrb (m_axil_wstrb),
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.s_axil_bvalid (m_axil_bvalid),
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.s_axil_bready (m_axil_bready),
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.s_axil_bresp (m_axil_bresp),
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.s_axil_arvalid (m_axil_arvalid),
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.s_axil_arready (m_axil_arready),
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.s_axil_araddr (m_axil_araddr),
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.s_axil_arprot (m_axil_arprot),
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.s_axil_rvalid (m_axil_rvalid),
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.s_axil_rready (m_axil_rready),
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.s_axil_rdata (m_axil_rdata),
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.s_axil_rresp (m_axil_rresp)
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);
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initial begin
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aresetn = 0;
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#1us aresetn = 1;
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end
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task send_cmd(input string cmd);
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begin
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foreach(cmd[i]) begin
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u0_vip_uart.send(cmd[i]);
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end
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end
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endtask
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initial begin
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#1ns;
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@(posedge aresetn);
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#1ms;
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send_cmd("\n");
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#5ms;
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send_cmd("r 0 -t\n");
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#20ms;
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send_cmd("\x03");
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#5ms;
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send_cmd("r 0 -t\n");
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#20ms;
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send_cmd("r\n");
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#20ms;
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send_cmd("\x03");
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#5ms;
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end
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endmodule
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