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uart/uart.sv

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+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+module uart
+#(
+    parameter integer CLOCK_FREQUENCY   = 50e6,
+    parameter integer BAUD_RATE         = 115200,
+    parameter logic CFG_PARITY_EN       = 1'b0,     // 0: disable parity;   1: enable parity
+    parameter logic CFG_EVEN_PARITY     = 1'b0,     // 0: odd parity;       1: even parity
+    parameter logic CFG_STOP_BIT        = 1'b0      // 0: 1 stop bit;       1: 2 stop bit
+)
+(
+    input  logic        clk,
+    input  logic        rstn,
+
+    input  logic        rx_i,      // Receiver input
+    output logic        tx_o,      // Transmitter output
+
+    output logic        rx_valid,
+    output logic [7:0]  rx_data,
+    input  logic        rx_ready,
+
+    input  logic        tx_valid,
+    input  logic [7:0]  tx_data,
+    output logic        tx_ready
+);
+    // register addresses
+
+    // TODO: check that stop bits are really not necessary here
+    uart_rx uart_rx_i
+    (
+        .clk_i              ( clk                           ),
+        .rstn_i             ( rstn                          ),
+        .rx_i               ( rx_i                          ),
+        .cfg_en_i           ( 1'b1                          ),
+        .cfg_div_i          ( CLOCK_FREQUENCY/BAUD_RATE     ),
+        .cfg_parity_en_i    ( CFG_PARITY_EN                 ),
+        .cfg_even_parity_i  ( CFG_EVEN_PARITY               ),
+        .busy_o             (                               ),
+        .parity_error_o     (                               ),
+        .overrun_o          (                               ),
+        .err_clr_i          ( 1'b1                          ),
+
+        .rx_data_o          ( rx_data                       ),
+        .rx_valid_o         ( rx_valid                      ),
+        .rx_ready_i         ( rx_ready                      )
+    );
+
+    uart_tx uart_tx_i
+    (
+        .clk_i              ( clk                           ),
+        .rstn_i             ( rstn                          ),
+        .tx_o               ( tx_o                          ),
+        .busy_o             (                               ),
+        .cfg_en_i           ( 1'b1                          ),
+        .cfg_div_i          ( CLOCK_FREQUENCY/BAUD_RATE     ),
+        .cfg_parity_en_i    ( CFG_PARITY_EN                 ),
+        .cfg_even_parity_i  ( CFG_EVEN_PARITY               ),
+        .cfg_stop_bits_i    ( CFG_STOP_BIT                  ),
+
+        .tx_data_i          ( tx_data                       ),
+        .tx_valid_i         ( tx_valid                      ),
+        .tx_ready_o         ( tx_ready                      )
+    );
+
+
+endmodule