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stream_tx_ctrl/sim/run_template.tcl
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227
stream_tx_ctrl/sim/run_template.tcl
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#quit -sim
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#ATTTION : MODIFY THIS FILE AS YOU WANT
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#ATTTION : MODIFY THIS FILE AS YOU WANT
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#ATTTION : MODIFY THIS FILE AS YOU WANT
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#ATTTION : MODIFY THIS FILE AS YOU WANT
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#ATTTION : MODIFY THIS FILE AS YOU WANT
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#unbound the the "work" lib dir from vsim,to remove it
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#when error do not save wave list
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if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
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source savewave.tcl
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}
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#catch {q -sim} res
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#dataset close -all
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echo on
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.main clear
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puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
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vmap std $SIM_TOOL_PATH/std ;
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vmap ieee $SIM_TOOL_PATH/ieee ;
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set FUNC_SOURCE_DIR ../../../01_source/01_func
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set TIMING_SOURCE_DIR ../../../01_source/02_timing
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set source_vhdl false
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set source_verilog false
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set LIB_OPTION ""
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set LOG_OPTION ""
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#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
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# #-----------actel----------
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# #puts "IDE IS $FPGA_KIT_VER!"
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# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
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# set LOG_OPTION "-vhdlvariablelogging"
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# }
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# if {[string equal -nocase vhd $TOP_FILE_LANG]} {
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# vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
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# } else {
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# vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
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# }
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# set LIB_OPTION "-L ${ACTEL_FAMILY}"
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#
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#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
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# #puts "IDE IS $FPGA_KIT_VER!"
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# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
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# set source_vhdl true
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# set LOG_OPTION "-vhdlvariablelogging"
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# }
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# foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
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# set source_verilog true
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# }
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# if { [string equal -nocase true $source_vhdl] } {
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# #-----------xilinx vhdl----------
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# #puts "vhdl file exist!"
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# vmap simprim $VHDL_LIB/simprim
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# vmap unisim $VHDL_LIB/unisim
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# vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
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# vmap unimacro $VHDL_LIB/unimacro
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# set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
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# }
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#
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# if { [string equal -nocase true $source_verilog] } {
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# #-----------xilinx verilog----------
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# #puts "verilog file exist!"
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# vmap unisims_ver $VLOG_LIB/unisims_ver
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# vmap simprims_ver $VLOG_LIB/simprims_ver
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# vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
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# vmap unimacro_ver $VLOG_LIB/unimacro_ver
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# vmap secureip $VLOG_LIB/secureip
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# set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
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# }
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#}
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set defs [dict create;] ;
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dict append defs CASE_NAME $CASE_NAME;
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dict append defs TOP_ENTITY $TOP_ENTITY;
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dict append defs TOP_INSTANCE $TOP_INSTANCE;
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dict append defs timing;
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dict append defs SIM_TIME $SIM_TIME ;
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set def_string "";
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dict for {def_name def_value} $defs {
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set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
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}
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puts "the define string is:$def_string"
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#file delete -force work ;
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vlib $WORK_LIB_DIR/${CASE_DIR};
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vmap work $WORK_LIB_DIR/${CASE_DIR};
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catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock } res;
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catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/ } res;
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#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
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#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
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#if {[info exists 1]} {
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# set SIM_TIME $1
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#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
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#by default,all cases use the same source file list
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set VLOG_SOURCE_LIST ../file_ver.f;
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set VHDL_SOURCE_LIST ../file_vhd.f;
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#we specify individual file list for single case
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if {[file exists file_ver.f ]} {
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puts "---->using case dependent verilog file list"
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set VLOG_SOURCE_LIST file_ver.f;
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}
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if {[file exists file_vhd.f ]} {
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puts "---->using case dependent vhdl file list"
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set VHDL_SOURCE_LIST file_vhd.f;
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}
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if {![string equal vhd $TOP_FILE_LANG]} {
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set GLBL glbl
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}
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if {$SIM_TYPE == "timing"} {
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set SDF_TYPE "-sdfmax";
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set SDFCOM_TYPE "-maxdelays";
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puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
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if {[string equal $CORNER_TYPE "01_min" ]} {
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set SDF_TYPE "-sdfmin";
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set SDFCOM_TYPE "-mindelays";
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puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
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} elseif {[string equal $CORNER_TYPE "02_type" ]} {
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set SDF_TYPE "-sdftyp";
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set SDFCOM_TYPE "-typdelays";
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puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
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} elseif {[string equal $CORNER_TYPE "03_max" ]} {
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set SDF_TYPE "-sdfmax";
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set SDFCOM_TYPE "-maxdelays";
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puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
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}
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if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
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puts "++++++++++ develop kit is libero ++++++++++";
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} else {
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puts "++++++++++ develop kit is not libero ++++++++++";
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set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
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}
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sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
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#in timing simulation ,here only glbl may be compiled seperately
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if {[file exists ${VLOG_SOURCE_LIST}]} {
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vlog -incr -quiet -sv +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
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}
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vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
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vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
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eval vopt ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
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+initmem+0 +initreg+0 +initwire+0;
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eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout \
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+no_notifier +no_tchk_msg\
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work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
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${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
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do ../suppresswarning.tcl
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catch {run ${SIM_TIME} } res
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} else {
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#compile source files
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if {[file exists ${VLOG_SOURCE_LIST}]} {
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puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
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# vlog -incr -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
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vlog -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
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}
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if {[file exists ${VHDL_SOURCE_LIST}]} {
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puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
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vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
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}
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# eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
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# +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
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# +initmem+0 +initreg+0 +initwire+0 \
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# -suppress 2912 \
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# -suppress 1127
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#to mask 211 error
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catch {
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if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
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eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
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-t 1ps -wlfopt -wlfcompress -nostdout \
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+initmem+0 +initreg+0 +initwire+0 \
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+no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
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-classdebug \
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glbl work.${CASE_NAME} \
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-wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
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} else {
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restart -f
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}
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} res;
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do ../suppresswarning.tcl
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catch {do wave.tcl} res
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set TEMP_REF_FILES info.txt;
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write report -l $TEMP_REF_FILES
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catch {run ${SIM_TIME} } res
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do ../saveucdb.tcl
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#}
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set current_path [pwd]
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puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
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