首次提交
This commit is contained in:
eesimple
826
stream_tx_buffer/src/component.xml
Normal file
826
stream_tx_buffer/src/component.xml
Normal file
@@ -0,0 +1,826 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>stream_tx_if</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>interface_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>buf_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">interface_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>desc_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>buf_if</spirit:name>
|
||||
<spirit:displayName>buf_if</spirit:displayName>
|
||||
<spirit:description>buf_if</spirit:description>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>DIN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_wdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>DOUT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_rdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_wea</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>buf_addr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>desc_if</spirit:name>
|
||||
<spirit:displayName>desc_if</spirit:displayName>
|
||||
<spirit:description>desc_if</spirit:description>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>DIN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_wdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>DOUT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_rdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_wea</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_addr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>SystemVerilog</spirit:language>
|
||||
<spirit:modelName>stream_tx_if</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>a46450fe</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>SystemVerilog</spirit:language>
|
||||
<spirit:modelName>stream_tx_if</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>a46450fe</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>900f4290</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>enable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>burst_time_interval</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>doorbell</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_status</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>counter_tx_beats</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>counter_tx_bursts</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) / 8) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) / 8) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_addr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:ceil(spirit:log(2,spirit:decode(id('MODELPARAM_VALUE.BUF_SIZE')))) - 1)">11</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_wea</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) / 8) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>desc_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>desc_addr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">11</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>desc_wea</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>desc_wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>desc_rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREQ_HZ">125000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BRAM_LATENCY</spirit:name>
|
||||
<spirit:displayName>Bram Latency</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BRAM_LATENCY">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>STREAM_WIDTH</spirit:name>
|
||||
<spirit:displayName>Stream Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STREAM_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUF_SIZE</spirit:name>
|
||||
<spirit:displayName>Buf Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUF_SIZE">4096</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DESC_TOTAL</spirit:name>
|
||||
<spirit:displayName>Desc Total</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DESC_TOTAL">256</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>stream_tx_if.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_432aa8a5</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>stream_tx_if.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/stream_tx_if_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_900f4290</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>stream_tx_if_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ">125000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BRAM_LATENCY</spirit:name>
|
||||
<spirit:displayName>Bram Latency</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BRAM_LATENCY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>STREAM_WIDTH</spirit:name>
|
||||
<spirit:displayName>Stream Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STREAM_WIDTH">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUF_SIZE</spirit:name>
|
||||
<spirit:displayName>Buf Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUF_SIZE">4096</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DESC_TOTAL</spirit:name>
|
||||
<spirit:displayName>Desc Total</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DESC_TOTAL">256</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">stream_tx_if_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>stream_tx_if_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:xpmLibraries>
|
||||
<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
|
||||
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
||||
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
|
||||
</xilinx:xpmLibraries>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-11-27T12:10:33Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="536828d3"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2ff6f6e4"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5c65c791"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b19f3140"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="fb4c72d7"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
314
stream_tx_buffer/src/stream_tx_if.sv
Normal file
314
stream_tx_buffer/src/stream_tx_if.sv
Normal file
@@ -0,0 +1,314 @@
|
||||
module stream_tx_if #(
|
||||
parameter FREQ_HZ = 125_000_000,
|
||||
parameter BRAM_LATENCY = 1, // 1: LATCH only, 2: +primitive or core out reg, 3: +primitive and core out reg, 4+: +pipeline
|
||||
parameter STREAM_WIDTH = 8,
|
||||
parameter BUF_SIZE = 4096, // in bytes
|
||||
parameter DESC_TOTAL = 256
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic enable,
|
||||
input logic [15:0] burst_time_interval, // us
|
||||
input logic [31:0] doorbell,
|
||||
|
||||
output logic [31:0] buf_status,
|
||||
output logic [31:0] counter_tx_beats,
|
||||
output logic [31:0] counter_tx_bursts,
|
||||
|
||||
// input stream interface
|
||||
output logic [STREAM_WIDTH-1:0] tdata,
|
||||
output logic tvalid,
|
||||
output logic tlast,
|
||||
output logic [STREAM_WIDTH/8-1:0] tkeep,
|
||||
output logic [STREAM_WIDTH/8-1:0] tstrb,
|
||||
input logic tready,
|
||||
|
||||
// buffer interface
|
||||
output logic buf_clk,
|
||||
output logic [$clog2(BUF_SIZE)-1:0] buf_addr,
|
||||
output logic [STREAM_WIDTH/8-1:0] buf_wea,
|
||||
output logic [STREAM_WIDTH-1:0] buf_wdata,
|
||||
input logic [STREAM_WIDTH-1:0] buf_rdata,
|
||||
|
||||
// reg interface
|
||||
output logic desc_clk,
|
||||
output logic [11:0] desc_addr,
|
||||
output logic [ 3:0] desc_wea,
|
||||
output logic [31:0] desc_wdata,
|
||||
input logic [31:0] desc_rdata
|
||||
);
|
||||
|
||||
localparam BUF_ADDR_WIDTH = $clog2(BUF_SIZE);
|
||||
localparam DESC_IDX_WIDTH = $clog2(DESC_TOTAL);
|
||||
|
||||
if (STREAM_WIDTH != 8 && STREAM_WIDTH != 16 && STREAM_WIDTH != 32 && STREAM_WIDTH != 64) begin
|
||||
$error("STREAM_WIDTH must be one of the following values: 8, 16, 32, 64!");
|
||||
end
|
||||
|
||||
localparam ADDR_STEP = STREAM_WIDTH / 8;
|
||||
|
||||
logic [15:0] burst_time_interval_latched;
|
||||
logic [15:0] timer_us;
|
||||
logic timer_enable;
|
||||
logic timeout;
|
||||
|
||||
typedef enum logic [2:0] {
|
||||
TX_INIT,
|
||||
TX_OFF,
|
||||
TX_IDLE,
|
||||
TX_SKIP,
|
||||
TX_DATA,
|
||||
TX_WAIT,
|
||||
TX_INTERVAL
|
||||
} tx_state_t;
|
||||
|
||||
tx_state_t tx_state, tx_state_next;
|
||||
|
||||
logic [$clog2(BRAM_LATENCY+1)-1:0] bram_latency_cnt;
|
||||
|
||||
logic ip_ready;
|
||||
logic burst_done;
|
||||
|
||||
logic [15:0] burst_len;
|
||||
logic [15:0] burst_beats;
|
||||
|
||||
logic [31:0] current_entry;
|
||||
logic [DESC_IDX_WIDTH-1:0] next_entry_index;
|
||||
|
||||
logic desc_wen;
|
||||
|
||||
assign buf_clk = clk;
|
||||
assign desc_clk = clk;
|
||||
assign buf_wdata = 0; // not used
|
||||
assign buf_wea = {STREAM_WIDTH/8{1'b0}};
|
||||
assign desc_wea = {4{desc_wen}};
|
||||
assign desc_wdata = 0;
|
||||
|
||||
// FSM: register update
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
tx_state <= TX_INIT;
|
||||
end else begin
|
||||
tx_state <= tx_state_next;
|
||||
end
|
||||
end
|
||||
|
||||
// FSM: next state logic
|
||||
always_comb begin
|
||||
tx_state_next = tx_state;
|
||||
|
||||
case (tx_state)
|
||||
TX_INIT: begin
|
||||
if (next_entry_index == DESC_TOTAL - 1)
|
||||
tx_state_next = TX_OFF;
|
||||
end
|
||||
TX_OFF: begin
|
||||
if (enable)
|
||||
tx_state_next = TX_IDLE;
|
||||
end
|
||||
|
||||
TX_IDLE: begin
|
||||
if (desc_addr != doorbell[11:0])
|
||||
tx_state_next = TX_SKIP;
|
||||
if (!enable)
|
||||
tx_state_next = TX_INIT;
|
||||
end
|
||||
|
||||
TX_SKIP: begin
|
||||
if (bram_latency_cnt >= BRAM_LATENCY - 1)
|
||||
tx_state_next = TX_DATA;
|
||||
if (!enable)
|
||||
tx_state_next = TX_INIT;
|
||||
end
|
||||
|
||||
TX_DATA: begin
|
||||
tx_state_next = TX_WAIT;
|
||||
if (!enable)
|
||||
tx_state_next = TX_INIT;
|
||||
end
|
||||
|
||||
TX_WAIT: begin
|
||||
if (tvalid && tready) begin
|
||||
if (burst_beats < burst_len)
|
||||
tx_state_next = TX_SKIP;
|
||||
else
|
||||
tx_state_next = TX_INTERVAL;
|
||||
end
|
||||
if (!enable)
|
||||
tx_state_next = TX_INIT;
|
||||
end
|
||||
|
||||
TX_INTERVAL: begin
|
||||
if (timeout) begin
|
||||
tx_state_next = TX_IDLE;
|
||||
end
|
||||
if (!enable)
|
||||
tx_state_next = TX_INIT;
|
||||
end
|
||||
|
||||
default: begin
|
||||
tx_state_next = TX_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// FSM: output logic
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
buf_addr <= 0;
|
||||
desc_addr <= 0;
|
||||
desc_wen <= 0;
|
||||
tvalid <= 0;
|
||||
tdata <= 0;
|
||||
tkeep <= 0;
|
||||
tstrb <= 0;
|
||||
tlast <= 0;
|
||||
ip_ready <= 0;
|
||||
burst_time_interval_latched <= 0;
|
||||
bram_latency_cnt <= 0;
|
||||
timer_enable <= 0;
|
||||
burst_len <= 0;
|
||||
burst_beats <= 0;
|
||||
burst_done <= 0;
|
||||
next_entry_index <= 0;
|
||||
counter_tx_beats <= 0;
|
||||
counter_tx_bursts <= 0;
|
||||
end else begin
|
||||
tvalid <= 0;
|
||||
tkeep <= 0;
|
||||
tstrb <= 0;
|
||||
tlast <= 0;
|
||||
|
||||
desc_wen <= 0;
|
||||
desc_addr <= next_entry_index;
|
||||
|
||||
bram_latency_cnt <= 0;
|
||||
|
||||
burst_done <= 0;
|
||||
|
||||
if (burst_done) begin
|
||||
desc_wen <= 1'b1;
|
||||
next_entry_index <= next_entry_index + 1'b1;
|
||||
counter_tx_bursts <= counter_tx_bursts + 1'b1;
|
||||
end
|
||||
|
||||
case (tx_state)
|
||||
TX_INIT: begin
|
||||
desc_wen <= 1'b1;
|
||||
next_entry_index <= next_entry_index + 1'b1;
|
||||
if (next_entry_index == DESC_TOTAL - 1) begin
|
||||
ip_ready <= 1'b1;
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_OFF: begin
|
||||
buf_addr <= 0;
|
||||
timer_enable <= 0;
|
||||
burst_beats <= 0;
|
||||
counter_tx_beats <= 0;
|
||||
counter_tx_bursts <= 0;
|
||||
end
|
||||
|
||||
TX_IDLE: begin
|
||||
burst_beats <= 0;
|
||||
if (|burst_time_interval)
|
||||
burst_time_interval_latched <= burst_time_interval;
|
||||
else
|
||||
burst_time_interval_latched <= 16'h1; // min 1us
|
||||
|
||||
if (desc_addr != doorbell[11:0]) begin
|
||||
buf_addr <= {current_entry[15:0], 4'h0};
|
||||
burst_len <= current_entry[27:16];
|
||||
end
|
||||
if (!enable) begin
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_SKIP: begin
|
||||
bram_latency_cnt <= bram_latency_cnt + 1'b1;
|
||||
if (bram_latency_cnt >= BRAM_LATENCY - 1) begin
|
||||
bram_latency_cnt <= 0;
|
||||
end
|
||||
if (!enable) begin
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_DATA: begin
|
||||
tvalid <= 1'b1;
|
||||
tkeep <= {ADDR_STEP{1'b1}};
|
||||
tstrb <= {ADDR_STEP{1'b1}};
|
||||
tlast <= (burst_beats == burst_len - 1);
|
||||
tdata <= buf_rdata;
|
||||
|
||||
buf_addr <= buf_addr + ADDR_STEP;
|
||||
burst_beats <= burst_beats + 1'b1;
|
||||
counter_tx_beats <= counter_tx_beats + 1'b1;
|
||||
if (!enable) begin
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_WAIT: begin
|
||||
if (tvalid && tready) begin
|
||||
tvalid <= 0;
|
||||
tkeep <= 0;
|
||||
tstrb <= 0;
|
||||
tlast <= 0;
|
||||
if (burst_beats >= burst_len) begin
|
||||
burst_beats <= 0;
|
||||
burst_done <= 1'b1;
|
||||
timer_enable <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
tvalid <= 1'b1;
|
||||
tkeep <= {ADDR_STEP{1'b1}};
|
||||
tstrb <= {ADDR_STEP{1'b1}};
|
||||
tlast <= tlast;
|
||||
end
|
||||
if (!enable) begin
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_INTERVAL: begin
|
||||
if (timeout) begin
|
||||
timer_enable <= 0;
|
||||
end
|
||||
if (!enable) begin
|
||||
next_entry_index <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
// Do nothing
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign timeout = (timer_us >= burst_time_interval_latched) && timer_enable;
|
||||
|
||||
wall_timer #(
|
||||
.MODULE_FREQ_HZ(FREQ_HZ),
|
||||
.US_WIDTH(16)
|
||||
) wall_timer_us_inst (
|
||||
.clk(clk),
|
||||
.rst(!rst_n),
|
||||
.enable(timer_enable),
|
||||
.resume(1'b0),
|
||||
.us(timer_us),
|
||||
.ms(),
|
||||
.sec(),
|
||||
.hour()
|
||||
);
|
||||
|
||||
assign current_entry = desc_rdata;
|
||||
|
||||
assign buf_status[15: 0] = {next_entry_index};
|
||||
assign buf_status[31:16] = {ip_ready, 8'h0};
|
||||
|
||||
endmodule
|
||||
243
stream_tx_buffer/src/wall_timer.sv
Normal file
243
stream_tx_buffer/src/wall_timer.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
//---------------------------------------------------------------------------------------
|
||||
// filename: wall_timer.sv
|
||||
// description: wall timer
|
||||
// author: leguoqing@paisat.cn
|
||||
//---------------------------------------------------------------------------------------
|
||||
|
||||
module wall_timer
|
||||
#(
|
||||
parameter MODULE_FREQ_HZ = 50e6,
|
||||
parameter US_WIDTH = 10,
|
||||
parameter MS_WIDTH = 0,
|
||||
parameter SEC_WIDTH = 0,
|
||||
parameter HOUR_WIDTH = 0
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
|
||||
input logic enable,
|
||||
input logic resume,
|
||||
output logic [(US_WIDTH>0 ? US_WIDTH-1 : 0):0] us,
|
||||
output logic [(MS_WIDTH>0 ? MS_WIDTH-1 : 0):0] ms,
|
||||
output logic [(SEC_WIDTH>0 ? SEC_WIDTH-1 : 0):0] sec,
|
||||
output logic [(HOUR_WIDTH>0 ? HOUR_WIDTH-1 : 0):0] hour
|
||||
);
|
||||
|
||||
if (MODULE_FREQ_HZ < 1e6) $error("ERROR: MODULE_FREQ_HZ < 1e6!");
|
||||
if (MS_WIDTH > 0 && US_WIDTH < 10) $error("ERROR: MS_WIDTH > 0 && US_WIDTH < 10!");
|
||||
if (SEC_WIDTH > 0 && MS_WIDTH < 10) $error("ERROR: SEC_WIDTH > 0 && MS_WIDTH < 10!");
|
||||
if (HOUR_WIDTH > 0 && SEC_WIDTH < 12) $error("ERROR: HOUR_WIDTH > 0 && SEC_WIDTH < 12!");
|
||||
|
||||
localparam integer FREQ_CLK_MHZ = MODULE_FREQ_HZ / 1e6;
|
||||
localparam integer CYCLE_WIDTH = $clog2(FREQ_CLK_MHZ);
|
||||
|
||||
logic [CYCLE_WIDTH-1:0] cycle_cnt;
|
||||
/* tick signals, better as output port ? */
|
||||
logic us_tick;
|
||||
logic ms_tick;
|
||||
logic sec_tick;
|
||||
logic hour_tick;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cycle_cnt <= 0;
|
||||
end else begin
|
||||
if (enable == 1 && resume == 0) begin
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
cycle_cnt <= 0;
|
||||
end
|
||||
end else begin
|
||||
cycle_cnt <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
`ifndef __MICROSATE_SIM__
|
||||
// us
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
us_tick <= 0;
|
||||
us <= 0;
|
||||
end else begin
|
||||
us_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
us_tick <= 1;
|
||||
end
|
||||
if (us_tick) begin
|
||||
us <= us + 1;
|
||||
if (MS_WIDTH == 0) begin
|
||||
if (us_tick && us != {US_WIDTH{1'b1}}) begin
|
||||
us <= us + 1;
|
||||
end
|
||||
end else begin
|
||||
if (us_tick) begin
|
||||
us <= us + 1;
|
||||
if (us == US_WIDTH'(999)) begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ms
|
||||
generate
|
||||
if (MS_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ms_tick <= 0;
|
||||
ms <= 0;
|
||||
end else begin
|
||||
ms_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (us_tick && us == US_WIDTH'(999)) begin
|
||||
ms_tick <= 1;
|
||||
end
|
||||
if (SEC_WIDTH == 0) begin
|
||||
if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
|
||||
ms <= ms + 1;
|
||||
end
|
||||
end else begin
|
||||
if (ms_tick) begin
|
||||
ms <= ms + 1;
|
||||
if (ms == MS_WIDTH'(999)) begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign ms_tick = 0;
|
||||
assign ms = 0;
|
||||
end
|
||||
endgenerate
|
||||
`else
|
||||
// us
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
us_tick <= 0;
|
||||
us <= 0;
|
||||
end else begin
|
||||
us_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
us_tick <= 1;
|
||||
end
|
||||
end else begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ms
|
||||
generate
|
||||
if (MS_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ms_tick <= 0;
|
||||
ms <= 0;
|
||||
end else begin
|
||||
ms_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (us_tick) begin
|
||||
ms_tick <= 1;
|
||||
end
|
||||
if (SEC_WIDTH == 0) begin
|
||||
if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
|
||||
ms <= ms + 1;
|
||||
end
|
||||
end else begin
|
||||
if (ms_tick) begin
|
||||
ms <= ms + 1;
|
||||
if (ms == MS_WIDTH'(999)) begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign ms_tick = 0;
|
||||
assign ms = 0;
|
||||
end
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
// sec
|
||||
generate
|
||||
if (SEC_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sec_tick <= 0;
|
||||
sec <= 0;
|
||||
end else begin
|
||||
sec_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (ms_tick && ms == MS_WIDTH'(999)) begin
|
||||
sec_tick <= 1;
|
||||
end
|
||||
if (HOUR_WIDTH == 0) begin
|
||||
if (sec_tick && sec != {SEC_WIDTH{1'b1}}) begin
|
||||
sec <= sec + 1;
|
||||
end
|
||||
end else begin
|
||||
if (sec_tick) begin
|
||||
sec <= sec + 1;
|
||||
if (sec == SEC_WIDTH'(3599)) begin
|
||||
sec <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
sec <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign sec_tick = 0;
|
||||
assign sec = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// hour
|
||||
generate
|
||||
if (HOUR_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hour_tick <= 0;
|
||||
hour <= 0;
|
||||
end else begin
|
||||
hour_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (sec_tick && sec == SEC_WIDTH'(3599)) begin
|
||||
hour_tick <= 1;
|
||||
end
|
||||
if (hour_tick && hour != {HOUR_WIDTH{1'b1}}) begin
|
||||
hour <= hour + 1;
|
||||
end
|
||||
end else begin
|
||||
hour <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign hour_tick = 0;
|
||||
assign hour = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
85
stream_tx_buffer/src/xgui/stream_tx_if_v1_0.tcl
Normal file
85
stream_tx_buffer/src/xgui/stream_tx_if_v1_0.tcl
Normal file
@@ -0,0 +1,85 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "BRAM_LATENCY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "BUF_SIZE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DESC_TOTAL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "FREQ_HZ" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "STREAM_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BRAM_LATENCY { PARAM_VALUE.BRAM_LATENCY } {
|
||||
# Procedure called to update BRAM_LATENCY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BRAM_LATENCY { PARAM_VALUE.BRAM_LATENCY } {
|
||||
# Procedure called to validate BRAM_LATENCY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BUF_SIZE { PARAM_VALUE.BUF_SIZE } {
|
||||
# Procedure called to update BUF_SIZE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BUF_SIZE { PARAM_VALUE.BUF_SIZE } {
|
||||
# Procedure called to validate BUF_SIZE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DESC_TOTAL { PARAM_VALUE.DESC_TOTAL } {
|
||||
# Procedure called to update DESC_TOTAL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DESC_TOTAL { PARAM_VALUE.DESC_TOTAL } {
|
||||
# Procedure called to validate DESC_TOTAL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to update FREQ_HZ when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to validate FREQ_HZ
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.STREAM_WIDTH { PARAM_VALUE.STREAM_WIDTH } {
|
||||
# Procedure called to update STREAM_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.STREAM_WIDTH { PARAM_VALUE.STREAM_WIDTH } {
|
||||
# Procedure called to validate STREAM_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.FREQ_HZ { MODELPARAM_VALUE.FREQ_HZ PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FREQ_HZ}] ${MODELPARAM_VALUE.FREQ_HZ}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BRAM_LATENCY { MODELPARAM_VALUE.BRAM_LATENCY PARAM_VALUE.BRAM_LATENCY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BRAM_LATENCY}] ${MODELPARAM_VALUE.BRAM_LATENCY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.STREAM_WIDTH { MODELPARAM_VALUE.STREAM_WIDTH PARAM_VALUE.STREAM_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.STREAM_WIDTH}] ${MODELPARAM_VALUE.STREAM_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BUF_SIZE { MODELPARAM_VALUE.BUF_SIZE PARAM_VALUE.BUF_SIZE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BUF_SIZE}] ${MODELPARAM_VALUE.BUF_SIZE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DESC_TOTAL { MODELPARAM_VALUE.DESC_TOTAL PARAM_VALUE.DESC_TOTAL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DESC_TOTAL}] ${MODELPARAM_VALUE.DESC_TOTAL}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user