首次提交

2026-03-06 16:22:17 +08:00
commit b8fe9f77ec
465 changed files with 115939 additions and 0 deletions
--- a/stream_tx_buffer/sim/func001/vip_clock.sv
+++ b/stream_tx_buffer/sim/func001/vip_clock.sv
@@ -0,0 +1,29 @@
+module vip_clock
+    #(
+    parameter FREQUENCY_MHZ = 1,
+    parameter PHASE_DEGREE = 0
+    )
+    (
+    input int duty_percent = 50,//dynamical parameter
+    input int jitter_percent = 0,//dynamical parameter
+    output clk
+    );
+
+
+
+logic ideal_clk;
+
+initial begin
+    ideal_clk = 0;
+    #(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
+    forever begin
+        ideal_clk = 0;
+        #(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);
+
+        ideal_clk = 1;
+        #(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
+    end
+end
+
+assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk =  ideal_clk;
+endmodule