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stream_tx_buffer/sim/func001/tb.sv

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+`timescale 1ns/1ps
+
+module
+    `CASE_NAME();
+    `include "../instantiate_top.sv"
+	
+	final mti_fli::mti_Cmd("do ../saveucdb.tcl");
+
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+/*to end the simulation commandary*/
+/*if you want to end the simulation case by case,just comment the line
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
+//TODO:
+
+    // instance vip
+    vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
+
+ 
+
+
+    initial begin
+        enable = 1'b1;
+        burst_time_interval = 8'h10;
+        
+        tready  = 1;
+
+        buf_rdata = 0;
+        doorbell = 4;
+
+        rst_n = 0;
+        #1us rst_n = 1;
+    end
+
+    always@(posedge clk) begin
+        case (list_addr)
+            'h0: list_rdata <= 32'h0040_0000; // len=64
+            'h1: list_rdata <= 32'h0080_0100; // len=128
+            'h2: list_rdata <= 32'h00C0_0200; // len=192
+            'h3: list_rdata <= 32'h0100_0300; // len=256
+            default: list_rdata <= 32'h0;
+        endcase
+    end
+
+    initial begin
+        #1ns;
+        @(posedge rst_n);
+        #10us;
+    end
+		
+endmodule