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825
stream_rx_buffer/src/component.xml
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825
stream_rx_buffer/src/component.xml
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>stream_rx_if</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
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||||
<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>interface_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TDATA</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TSTRB</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tstrb</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TKEEP</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tkeep</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TLAST</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tlast</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TVALID</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tvalid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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||||
<spirit:physicalPort>
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<spirit:name>tready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>rst_n</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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||||
<spirit:physicalPort>
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<spirit:name>rst_n</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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||||
<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>buf_clk</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>buf_clk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>clk</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
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||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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||||
<spirit:name>clk</spirit:name>
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</spirit:physicalPort>
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||||
</spirit:portMap>
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</spirit:portMaps>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">interface_axis</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>desc_clk</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
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||||
<spirit:portMaps>
|
||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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||||
<spirit:name>desc_clk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>buf_if</spirit:name>
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<spirit:displayName>buf_if</spirit:displayName>
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||||
<spirit:description>buf_if</spirit:description>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>DIN</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>buf_wdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>DOUT</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>buf_rdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>buf_clk</spirit:name>
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</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>WE</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>buf_wea</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>ADDR</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>buf_addr</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>desc_if</spirit:name>
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||||
<spirit:displayName>desc_if</spirit:displayName>
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||||
<spirit:description>desc_if</spirit:description>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>DIN</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>desc_wdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>DOUT</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>desc_rdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CLK</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>desc_clk</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
|
||||
<spirit:name>WE</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>desc_wea</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>ADDR</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>desc_addr</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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||||
<spirit:language>SystemVerilog</spirit:language>
|
||||
<spirit:modelName>stream_rx_if</spirit:modelName>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>a39eba53</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>SystemVerilog</spirit:language>
|
||||
<spirit:modelName>stream_rx_if</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>a39eba53</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7d5f69bb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>enable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>max_resp_time</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>buf_status</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>counter_rx_beats</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>counter_rx_bursts</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>counter_rx_segments</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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<spirit:wireTypeDef>
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>tvalid</spirit:name>
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<spirit:wireTypeDef>
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:wireTypeDef>
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:wireTypeDef>
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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<spirit:name>tready</spirit:name>
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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||||
<spirit:port>
|
||||
<spirit:name>buf_clk</spirit:name>
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||||
<spirit:direction>out</spirit:direction>
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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||||
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||||
<spirit:port>
|
||||
<spirit:name>buf_addr</spirit:name>
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||||
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||||
<spirit:direction>out</spirit:direction>
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||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:ceil(spirit:log(2,spirit:decode(id('MODELPARAM_VALUE.BUF_SIZE')))) - 1)">11</spirit:left>
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||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>buf_wea</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) / 8) - 1)">0</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>buf_wdata</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
<spirit:port>
|
||||
<spirit:name>buf_rdata</spirit:name>
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||||
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|
||||
<spirit:direction>in</spirit:direction>
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||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.STREAM_WIDTH')) - 1)">7</spirit:left>
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||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>desc_clk</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
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||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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||||
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>desc_addr</spirit:name>
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||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">11</spirit:left>
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||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
|
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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|
||||
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>desc_wea</spirit:name>
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||||
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|
||||
<spirit:direction>out</spirit:direction>
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||||
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|
||||
<spirit:left spirit:format="long">3</spirit:left>
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||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
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|
||||
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|
||||
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|
||||
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>desc_wdata</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
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||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>desc_rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">31</spirit:left>
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||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREQ_HZ">125000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>STREAM_WIDTH</spirit:name>
|
||||
<spirit:displayName>Stream Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STREAM_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>BUF_SIZE</spirit:name>
|
||||
<spirit:displayName>Buf Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BUF_SIZE">4096</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SEG_SIZE</spirit:name>
|
||||
<spirit:displayName>Seg Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEG_SIZE">256</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
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||||
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<spirit:choice>
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||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
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||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>stream_rx_if.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
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||||
<spirit:userFileType>CHECKSUM_4e3b52a1</spirit:userFileType>
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</spirit:file>
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<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>stream_rx_if.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/stream_rx_if_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_7d5f69bb</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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||||
</spirit:file>
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||||
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||||
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||||
<spirit:description>stream_rx_if_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ">125000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>STREAM_WIDTH</spirit:name>
|
||||
<spirit:displayName>Stream Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STREAM_WIDTH">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BUF_SIZE</spirit:name>
|
||||
<spirit:displayName>Buf Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BUF_SIZE">4096</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SEG_SIZE</spirit:name>
|
||||
<spirit:displayName>Seg Size</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SEG_SIZE">256</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">stream_rx_if_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
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||||
<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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<xilinx:displayName>stream_rx_if_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:xpmLibraries>
|
||||
<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
|
||||
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
||||
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
|
||||
</xilinx:xpmLibraries>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-11-23T11:42:29Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0df276c1"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3f883063"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="bef9fbfb"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e33e78a7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="82cd03bc"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
Reference in New Issue
Block a user