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stream_rx_buffer/sim/func001/tb.sv

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+`timescale 1ns/1ps
+
+module
+    `CASE_NAME();
+    `include "../instantiate_top.sv"
+	
+	final mti_fli::mti_Cmd("do ../saveucdb.tcl");
+
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+/*to end the simulation commandary*/
+/*if you want to end the simulation case by case,just comment the line
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
+//TODO:
+
+    // instance vip
+    vip_clock # (.FREQUENCY_MHZ(125)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
+
+ 
+
+
+    initial begin
+        enable = 1'b1;
+        max_resp_time = 8'h1;
+        
+        tvalid = 0;
+        tdata  = 0;
+        tkeep  = 0;
+        tstrb  = 0;
+        tlast  = 0;
+
+        rst_n = 0;
+        #1us rst_n = 1;
+    end
+
+    task send_stream(input int number_of_beats, input int beat_cycle = 8, input logic last_beat_valid = 1);
+        begin
+            repeat(number_of_beats-last_beat_valid) begin
+                @(posedge clk);
+                tvalid = 1'b1;
+                tdata  = $urandom;
+                tkeep  = 1'b1;
+                tstrb  = 1'b1;
+                tlast  = 1'b0;
+                repeat(beat_cycle-1) begin
+                    @(posedge clk);
+                    tvalid = 0;
+                    tdata  = 0;
+                    tkeep  = 0;
+                    tstrb  = 0;
+                    tlast  = 0;
+                end
+            end
+            
+            if (last_beat_valid) begin
+                @(posedge clk);
+                tvalid = 1'b1;
+                tdata  = $urandom;
+                tkeep  = 1'b1;
+                tstrb  = 1'b1;
+                tlast  = 1'b1;
+                repeat(beat_cycle-1) begin
+                    @(posedge clk);
+                    tvalid = 0;
+                    tdata  = 0;
+                    tkeep  = 0;
+                    tstrb  = 0;
+                    tlast  = 0;
+                end
+            end else begin
+                @(posedge clk);
+                tvalid = 1;
+                tdata  = 0;
+                tkeep  = 0;
+                tstrb  = 0;
+                tlast  = 1;
+
+                repeat(beat_cycle-1) begin
+                    @(posedge clk);
+                    tvalid = 0;
+                    tdata  = 0;
+                    tkeep  = 0;
+                    tstrb  = 0;
+                    tlast  = 0;
+                end
+            end
+
+            @(posedge clk);
+            tvalid = 0;
+            tdata  = 0;
+            tkeep  = 0;
+            tstrb  = 0;
+            tlast  = 0;
+        end
+    endtask
+
+    initial begin
+        #1ns;
+        @(posedge rst_n);
+        #10us;
+        send_stream(16);
+        #50us;
+        send_stream(20);
+        #100us;
+        send_stream(8);
+        #1ms;
+
+        send_stream(800);
+        #10us;
+        send_stream(300);
+    end
+		
+endmodule