leguoqing/FPGA_DESIGN_IP
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eesimple
2026-03-06 16:22:17 +08:00
commit b8fe9f77ec
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stream_rx_buffer/sim/file_ver.f Normal file
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//+define+__MICROSATE_SIM__
vip_clock.sv
vip_uart.sv
axil_ram.v
tb.sv
../glbl.v
../../src/stream_rx_if.sv
../../src/wall_timer.sv