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537
ssp_tx/src/component.xml
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537
ssp_tx/src/component.xml
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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<spirit:name>ssp_tx</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
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||||
<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>interface_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TDATA</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>tdata</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TSTRB</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tstrb</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TKEEP</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>tkeep</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TLAST</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>tlast</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TVALID</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>tvalid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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||||
<spirit:physicalPort>
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<spirit:name>tready</spirit:name>
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</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>aresetn</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>clk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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||||
<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>clk</spirit:name>
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</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">interface_axis</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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||||
</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
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||||
<spirit:views>
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<spirit:view>
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||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>SystemVerilog</spirit:language>
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<spirit:modelName>ssp_tx</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>888b0c15</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:language>SystemVerilog</spirit:language>
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||||
<spirit:modelName>ssp_tx</spirit:modelName>
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<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>888b0c15</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_xpgui</spirit:name>
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||||
<spirit:displayName>UI Layout</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>73301cb5</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
</spirit:views>
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||||
<spirit:ports>
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||||
<spirit:port>
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||||
<spirit:name>clk</spirit:name>
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<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
|
||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>tdata</spirit:name>
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||||
<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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||||
<spirit:vector>
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||||
<spirit:left spirit:format="long">7</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
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||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
<spirit:driver>
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||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
</spirit:driver>
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>tvalid</spirit:name>
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||||
<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>tkeep</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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||||
</spirit:driver>
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||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tstrb</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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||||
</spirit:driver>
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||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ssp_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ssp_csn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ssp_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ssp_tx_busy</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>config_00</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>config_01</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_00</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_01</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_02</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREQ_HZ">100000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SSP_HZ</spirit:name>
|
||||
<spirit:displayName>Ssp Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SSP_HZ">10000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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||||
</spirit:choice>
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||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>ssp_tx.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_ce7decc3</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>wall_timer.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>ssp_tx.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/ssp_tx_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_73301cb5</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>ssp_tx_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Freq Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SSP_HZ</spirit:name>
|
||||
<spirit:displayName>Ssp Hz</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSP_HZ">10000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ssp_tx_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
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<xilinx:displayName>ssp_tx_v1_0</xilinx:displayName>
|
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:coreRevision>2</xilinx:coreRevision>
|
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<xilinx:coreCreationDateTime>2026-02-03T10:02:02Z</xilinx:coreCreationDateTime>
|
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<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
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</xilinx:tags>
|
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</xilinx:coreExtensions>
|
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<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
|
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="d9ac155a"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7ef768ec"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="66c181c2"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f333f548"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="25c05a5c"/>
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||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
266
ssp_tx/src/ssp_tx.sv
Normal file
266
ssp_tx/src/ssp_tx.sv
Normal file
@@ -0,0 +1,266 @@
|
||||
//---------------------------------------------------------------------------------------
|
||||
// filename: ssp_tx.sv
|
||||
// description: synchronous serial peripheral interface transmitter
|
||||
// author: leguoqing@paisat.cn
|
||||
//---------------------------------------------------------------------------------------
|
||||
|
||||
module ssp_tx #(
|
||||
parameter integer FREQ_HZ = 100e6,
|
||||
parameter integer SSP_HZ = 10e6
|
||||
) (
|
||||
input logic clk,
|
||||
input logic aresetn,
|
||||
|
||||
input logic [7:0] tdata,
|
||||
input logic tvalid,
|
||||
input logic tkeep,
|
||||
input logic tstrb,
|
||||
input logic tlast,
|
||||
output logic tready,
|
||||
|
||||
output logic ssp_clk,
|
||||
output logic ssp_csn,
|
||||
output logic ssp_data,
|
||||
|
||||
output logic ssp_tx_busy,
|
||||
|
||||
input logic [31:0] config_00,
|
||||
input logic [31:0] config_01,
|
||||
|
||||
output logic [31:0] status_00,
|
||||
output logic [31:0] status_01,
|
||||
output logic [31:0] status_02
|
||||
);
|
||||
|
||||
if ($ceil(FREQ_HZ/SSP_HZ) != $floor(FREQ_HZ/SSP_HZ)) begin
|
||||
$fatal("%m: FREQ_HZ must be an integer multiple of SSP_HZ!");
|
||||
end else if (FREQ_HZ/SSP_HZ < 6) begin
|
||||
$fatal("%m: FREQ_HZ/SSP_HZ < 6!");
|
||||
end else if ((FREQ_HZ/SSP_HZ)%2 != 0) begin
|
||||
$warning("%m: FREQ_HZ/SSP_HZ is not an even number, which means the SSP clock will be asymmetric!");
|
||||
end
|
||||
|
||||
localparam integer CLK_HI = $ceil(FREQ_HZ/(2*SSP_HZ));
|
||||
localparam integer CLK_LO = $floor(FREQ_HZ/(2*SSP_HZ));
|
||||
|
||||
localparam integer SEP_BYTES = 1; // Number of byte times to wait between transmissions
|
||||
localparam integer TIMER_US_WIDTH = 32;
|
||||
|
||||
// State encoding
|
||||
typedef enum logic [1:0] {
|
||||
IDLE,
|
||||
TRANSMIT,
|
||||
LAST,
|
||||
SEP
|
||||
} state_t;
|
||||
|
||||
state_t state, state_next;
|
||||
|
||||
logic [ 7:0] fsm_hardcode;
|
||||
logic [31:0] counter_tx_data;
|
||||
logic [31:0] counter_tx_last;
|
||||
|
||||
// Clock divider
|
||||
logic [23:0] clk_div;
|
||||
|
||||
logic [7:0] tx_shift_reg;
|
||||
logic [2:0] tx_bit_cnt;
|
||||
logic [23:0] last_divider;
|
||||
|
||||
logic timer_enable;
|
||||
logic timeout;
|
||||
logic [TIMER_US_WIDTH-1:0] timer_us;
|
||||
|
||||
logic [TIMER_US_WIDTH-1:0] min_sep_us;
|
||||
logic [23:0] cfg_divider;
|
||||
|
||||
assign min_sep_us = config_00[0+:TIMER_US_WIDTH];
|
||||
assign cfg_divider = config_01;
|
||||
|
||||
assign status_00 = {16'h0, fsm_hardcode, 8'h1};
|
||||
assign status_01 = counter_tx_data;
|
||||
assign status_02 = counter_tx_last;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (~aresetn) begin
|
||||
fsm_hardcode <= 0;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE:
|
||||
fsm_hardcode <= 8'h0;
|
||||
TRANSMIT:
|
||||
fsm_hardcode <= 8'h1;
|
||||
LAST:
|
||||
fsm_hardcode <= 8'h2;
|
||||
SEP:
|
||||
fsm_hardcode <= 8'h3;
|
||||
default:
|
||||
fsm_hardcode <= 8'hF;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// FSM: State register
|
||||
always_ff @(posedge clk) begin
|
||||
if (!aresetn) begin
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
state <= state_next;
|
||||
end
|
||||
end
|
||||
|
||||
// FSM: Next state logic
|
||||
always_comb begin
|
||||
state_next = state;
|
||||
case (state)
|
||||
IDLE: begin
|
||||
if (tvalid & tkeep && clk_div == last_divider) begin
|
||||
if (tlast)
|
||||
state_next = LAST;
|
||||
else
|
||||
state_next = TRANSMIT;
|
||||
end
|
||||
end
|
||||
TRANSMIT: begin
|
||||
if (tx_bit_cnt == 3'h7 && clk_div == last_divider) begin
|
||||
if (tvalid)
|
||||
if (tkeep && tlast)
|
||||
state_next = LAST;
|
||||
else if (!tkeep)
|
||||
state_next = SEP;
|
||||
end
|
||||
end
|
||||
LAST: begin
|
||||
if (tx_bit_cnt == 3'h7 && clk_div == last_divider)
|
||||
state_next = SEP; // Go to SEP state after last bit transmitted
|
||||
end
|
||||
SEP: begin
|
||||
if (timeout)
|
||||
state_next = IDLE; // Go to IDLE after a short separation
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// FSM: Output logic
|
||||
always_ff @(posedge clk) begin
|
||||
if (!aresetn) begin
|
||||
tx_shift_reg <= 8'h0;
|
||||
tx_bit_cnt <= 3'h0;
|
||||
last_divider <= CLK_HI + CLK_LO - 1;
|
||||
tready <= 1'b0;
|
||||
ssp_clk <= 1'b0;
|
||||
clk_div <= 'h0;
|
||||
ssp_csn <= 1'b1;
|
||||
timer_enable <= 1'b0;
|
||||
end else begin
|
||||
tready <= 1'b0;
|
||||
ssp_clk <= 1'b0;
|
||||
ssp_csn <= 1'b1;
|
||||
|
||||
clk_div <= clk_div + 1'b1;
|
||||
if (clk_div < last_divider>>1)
|
||||
ssp_clk <= 1'b1;
|
||||
if (clk_div == last_divider) begin
|
||||
ssp_clk <= 1'b1;
|
||||
clk_div <= 'h0;
|
||||
end
|
||||
|
||||
case (state)
|
||||
IDLE: begin
|
||||
tx_bit_cnt <= 3'h0;
|
||||
timer_enable <= 1'b0;
|
||||
if (clk_div == 0) begin // to eliminate clk glitch when changing divider
|
||||
if (cfg_divider <= 10 - 1) begin
|
||||
last_divider <= CLK_HI + CLK_LO - 1;
|
||||
end else begin
|
||||
last_divider <= cfg_divider;
|
||||
end
|
||||
end
|
||||
if (tvalid && clk_div == last_divider) begin
|
||||
tready <= 1'b1;
|
||||
if (tkeep) begin
|
||||
tx_shift_reg <= tdata;
|
||||
ssp_csn <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
TRANSMIT: begin
|
||||
ssp_csn <= 1'b0;
|
||||
|
||||
if (clk_div == last_divider) begin
|
||||
tx_shift_reg <= {tx_shift_reg[6:0], 1'b0}; // Shift left
|
||||
tx_bit_cnt <= tx_bit_cnt + 3'h1;
|
||||
if (tx_bit_cnt == 3'h7) begin
|
||||
tx_bit_cnt <= 3'h0;
|
||||
if (tvalid) begin
|
||||
tready <= 1'b1;
|
||||
if (tkeep) begin
|
||||
tx_shift_reg <= tdata; // Load new data if available
|
||||
end else begin
|
||||
ssp_csn <= 1'b1;
|
||||
timer_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
LAST: begin
|
||||
ssp_csn <= 1'b0;
|
||||
|
||||
if (clk_div == last_divider) begin
|
||||
tx_shift_reg <= {tx_shift_reg[6:0], 1'b0}; // Shift left
|
||||
tx_bit_cnt <= tx_bit_cnt + 3'h1;
|
||||
if (tx_bit_cnt == 3'h7) begin
|
||||
tx_bit_cnt <= 3'h0;
|
||||
ssp_csn <= 1'b1;
|
||||
timer_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
SEP: begin
|
||||
if (timeout) begin
|
||||
timer_enable <= 0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign ssp_data = tx_shift_reg[7];
|
||||
|
||||
assign ssp_tx_busy = ~ssp_csn;
|
||||
|
||||
|
||||
// Counters for transmitted data and last signals
|
||||
always_ff @(posedge clk) begin
|
||||
if (!aresetn) begin
|
||||
counter_tx_data <= 32'h0;
|
||||
counter_tx_last <= 32'h0;
|
||||
end else begin
|
||||
if (tvalid && tready && tkeep) begin
|
||||
counter_tx_data <= counter_tx_data + 32'h1;
|
||||
end
|
||||
if (tvalid && tready && tlast) begin
|
||||
counter_tx_last <= counter_tx_last + 32'h1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign timeout = (timer_us >= min_sep_us) && timer_enable;
|
||||
|
||||
wall_timer #(
|
||||
.MODULE_FREQ_HZ(FREQ_HZ),
|
||||
.US_WIDTH(TIMER_US_WIDTH)
|
||||
) wall_timer_us_inst (
|
||||
.clk(clk),
|
||||
.rst(!aresetn),
|
||||
.enable(timer_enable),
|
||||
.resume(1'b0),
|
||||
.us(timer_us),
|
||||
.ms(),
|
||||
.sec(),
|
||||
.hour()
|
||||
);
|
||||
|
||||
endmodule
|
||||
243
ssp_tx/src/wall_timer.sv
Normal file
243
ssp_tx/src/wall_timer.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
//---------------------------------------------------------------------------------------
|
||||
// filename: wall_timer.sv
|
||||
// description: wall timer
|
||||
// author: leguoqing@paisat.cn
|
||||
//---------------------------------------------------------------------------------------
|
||||
|
||||
module wall_timer
|
||||
#(
|
||||
parameter MODULE_FREQ_HZ = 50e6,
|
||||
parameter US_WIDTH = 10,
|
||||
parameter MS_WIDTH = 0,
|
||||
parameter SEC_WIDTH = 0,
|
||||
parameter HOUR_WIDTH = 0
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
|
||||
input logic enable,
|
||||
input logic resume,
|
||||
output logic [(US_WIDTH>0 ? US_WIDTH-1 : 0):0] us,
|
||||
output logic [(MS_WIDTH>0 ? MS_WIDTH-1 : 0):0] ms,
|
||||
output logic [(SEC_WIDTH>0 ? SEC_WIDTH-1 : 0):0] sec,
|
||||
output logic [(HOUR_WIDTH>0 ? HOUR_WIDTH-1 : 0):0] hour
|
||||
);
|
||||
|
||||
if (MODULE_FREQ_HZ < 1e6) $error("ERROR: MODULE_FREQ_HZ < 1e6!");
|
||||
if (MS_WIDTH > 0 && US_WIDTH < 10) $error("ERROR: MS_WIDTH > 0 && US_WIDTH < 10!");
|
||||
if (SEC_WIDTH > 0 && MS_WIDTH < 10) $error("ERROR: SEC_WIDTH > 0 && MS_WIDTH < 10!");
|
||||
if (HOUR_WIDTH > 0 && SEC_WIDTH < 12) $error("ERROR: HOUR_WIDTH > 0 && SEC_WIDTH < 12!");
|
||||
|
||||
localparam integer FREQ_CLK_MHZ = MODULE_FREQ_HZ / 1e6;
|
||||
localparam integer CYCLE_WIDTH = $clog2(FREQ_CLK_MHZ);
|
||||
|
||||
logic [CYCLE_WIDTH-1:0] cycle_cnt;
|
||||
/* tick signals, better as output port ? */
|
||||
logic us_tick;
|
||||
logic ms_tick;
|
||||
logic sec_tick;
|
||||
logic hour_tick;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cycle_cnt <= 0;
|
||||
end else begin
|
||||
if (enable == 1 && resume == 0) begin
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
cycle_cnt <= 0;
|
||||
end
|
||||
end else begin
|
||||
cycle_cnt <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
`ifndef __MICROSATE_SIM__
|
||||
// us
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
us_tick <= 0;
|
||||
us <= 0;
|
||||
end else begin
|
||||
us_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
us_tick <= 1;
|
||||
end
|
||||
if (us_tick) begin
|
||||
us <= us + 1;
|
||||
if (MS_WIDTH == 0) begin
|
||||
if (us_tick && us != {US_WIDTH{1'b1}}) begin
|
||||
us <= us + 1;
|
||||
end
|
||||
end else begin
|
||||
if (us_tick) begin
|
||||
us <= us + 1;
|
||||
if (us == US_WIDTH'(999)) begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ms
|
||||
generate
|
||||
if (MS_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ms_tick <= 0;
|
||||
ms <= 0;
|
||||
end else begin
|
||||
ms_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (us_tick && us == US_WIDTH'(999)) begin
|
||||
ms_tick <= 1;
|
||||
end
|
||||
if (SEC_WIDTH == 0) begin
|
||||
if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
|
||||
ms <= ms + 1;
|
||||
end
|
||||
end else begin
|
||||
if (ms_tick) begin
|
||||
ms <= ms + 1;
|
||||
if (ms == MS_WIDTH'(999)) begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign ms_tick = 0;
|
||||
assign ms = 0;
|
||||
end
|
||||
endgenerate
|
||||
`else
|
||||
// us
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
us_tick <= 0;
|
||||
us <= 0;
|
||||
end else begin
|
||||
us_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
|
||||
us_tick <= 1;
|
||||
end
|
||||
end else begin
|
||||
us <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ms
|
||||
generate
|
||||
if (MS_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ms_tick <= 0;
|
||||
ms <= 0;
|
||||
end else begin
|
||||
ms_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (us_tick) begin
|
||||
ms_tick <= 1;
|
||||
end
|
||||
if (SEC_WIDTH == 0) begin
|
||||
if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
|
||||
ms <= ms + 1;
|
||||
end
|
||||
end else begin
|
||||
if (ms_tick) begin
|
||||
ms <= ms + 1;
|
||||
if (ms == MS_WIDTH'(999)) begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
ms <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign ms_tick = 0;
|
||||
assign ms = 0;
|
||||
end
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
// sec
|
||||
generate
|
||||
if (SEC_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
sec_tick <= 0;
|
||||
sec <= 0;
|
||||
end else begin
|
||||
sec_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (ms_tick && ms == MS_WIDTH'(999)) begin
|
||||
sec_tick <= 1;
|
||||
end
|
||||
if (HOUR_WIDTH == 0) begin
|
||||
if (sec_tick && sec != {SEC_WIDTH{1'b1}}) begin
|
||||
sec <= sec + 1;
|
||||
end
|
||||
end else begin
|
||||
if (sec_tick) begin
|
||||
sec <= sec + 1;
|
||||
if (sec == SEC_WIDTH'(3599)) begin
|
||||
sec <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
sec <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign sec_tick = 0;
|
||||
assign sec = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// hour
|
||||
generate
|
||||
if (HOUR_WIDTH > 0) begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hour_tick <= 0;
|
||||
hour <= 0;
|
||||
end else begin
|
||||
hour_tick <= 0;
|
||||
if (enable == 1 && resume == 0) begin
|
||||
if (sec_tick && sec == SEC_WIDTH'(3599)) begin
|
||||
hour_tick <= 1;
|
||||
end
|
||||
if (hour_tick && hour != {HOUR_WIDTH{1'b1}}) begin
|
||||
hour <= hour + 1;
|
||||
end
|
||||
end else begin
|
||||
hour <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
assign hour_tick = 0;
|
||||
assign hour = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
40
ssp_tx/src/xgui/ssp_tx_v1_0.tcl
Normal file
40
ssp_tx/src/xgui/ssp_tx_v1_0.tcl
Normal file
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "FREQ_HZ" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SSP_HZ" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to update FREQ_HZ when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to validate FREQ_HZ
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SSP_HZ { PARAM_VALUE.SSP_HZ } {
|
||||
# Procedure called to update SSP_HZ when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SSP_HZ { PARAM_VALUE.SSP_HZ } {
|
||||
# Procedure called to validate SSP_HZ
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.FREQ_HZ { MODELPARAM_VALUE.FREQ_HZ PARAM_VALUE.FREQ_HZ } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FREQ_HZ}] ${MODELPARAM_VALUE.FREQ_HZ}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SSP_HZ { MODELPARAM_VALUE.SSP_HZ PARAM_VALUE.SSP_HZ } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SSP_HZ}] ${MODELPARAM_VALUE.SSP_HZ}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user