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ssp_tx/sim/func001/tb.sv

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+`timescale 1ns/1ps
+
+module
+    `CASE_NAME();
+    `include "../instantiate_top.sv"
+	
+	final mti_fli::mti_Cmd("do ../saveucdb.tcl");
+
+    initial begin
+      $fsdbDumpfile("fsdb_wave.fsdb");
+      $fsdbDumpvars;
+    end
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+/*to end the simulation commandary*/
+/*if you want to end the simulation case by case,just comment the line
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
+//TODO:
+
+
+    logic [7:0]  ssp_rx_tdata;
+    logic        ssp_rx_tvalid;
+    logic        ssp_rx_tready = 0;
+    logic [31:0] error_status;
+
+    // instance vip
+    vip_clock # (.FREQUENCY_MHZ(100)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
+    
+    vip_clock # (.FREQUENCY_MHZ(110)) u1_clock(.duty_percent(50), .jitter_percent(0), .clk(ssp_rx_clk));
+
+    ssp_rx # (
+        .FREQ_HZ(110e6),
+        .SSP_HZ(10e6)
+    ) u_ssp_rx (
+        .clk        (ssp_rx_clk),
+        .aresetn    (aresetn),
+
+        .tdata      (ssp_rx_tdata),
+        .tvalid     (ssp_rx_tvalid),
+        .tready     (ssp_rx_tready),
+
+        .ssp_clk    (ssp_clk),
+        .ssp_csn    (ssp_csn),
+        .ssp_data   (ssp_data),
+
+        .error_status (error_status)
+    );
+
+    initial begin
+        aresetn = 1'b0;
+        #200ns;
+        aresetn = 1'b1;
+    end
+
+    initial begin
+        tdata  = 8'h00;
+        tvalid = 1'b0;
+        wait (!aresetn);
+        #100ns;
+
+        repeat (20) begin
+            // send a byte
+            tvalid = 1'b1;
+            @(posedge tready) #1ns;
+            tvalid = 1'b0;
+            tdata++;
+        end
+
+        //$finish;
+    end
+
+		
+endmodule