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ssp_tx/sim/func001/addwave.tcl

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+echo off
+#useage do addwave.tcl uart,where uart is a module name
+#when there is mulitple matches,the 1st one is picked
+puts "---->find by design unit:$1"
+
+set patten  *$1*;
+#puts "---->find patten:$patten"
+
+set rslt [find instance -bydu $patten];
+#puts "---->find result:$rslt"
+
+regsub {\{} $rslt "" rslt;
+regsub {\}} $rslt "" rslt;
+
+regsub { (.*)} $rslt "" path;
+#puts "---->design path is:$path"
+
+set signal_list ${path}/*
+puts "---->list to be add to wave:$signal_list"
+
+add wave $signal_list

ssp_tx/sim/func001/can_transceiver.sv

@@ -0,0 +1,22 @@
+/*
+	can bus physical model by leguoqing
+*/
+
+module can_transceiver
+	(
+		output logic rxd = 1,
+		input  logic txd,
+		inout  tri1  line
+	);
+
+	always@(*)
+		if (line == 1'b0) rxd <= 1'b0;
+		else rxd <= 1'b1;
+
+	logic line_reg;
+	always@(*)
+		if (txd == 0) line_reg <= 0;
+		else line_reg <= 1;
+
+	assign line = line_reg ? 1'bz : 0;
+endmodule

ssp_tx/sim/func001/cmsdk_uart_capture_ard.v

@@ -0,0 +1,254 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2010-2013 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2013-02-08 10:40:04 +0000 (Fri, 08 Feb 2013) $
+//
+//      Revision            : $Revision: 365823 $
+//
+//      Release Information : CM3DesignStart-r0p0-02rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK).  In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY    Capture XY to AUXCTRL output
+// ESC - 0x11         Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12         Clear DEBUG_TESTER_ENABLE to 0
+
+
+module cmsdk_uart_capture_ard (
+  input  wire       RESETn,              // Power on reset
+  input  wire       CLK,                 // Clock (baud rate)
+  input  wire       RXD,                 // Received data
+  output wire       SIMULATIONEND,       // Simulation end indicator
+  output wire       DEBUG_TESTER_ENABLE, // Enable debug tester
+  output wire [7:0] AUXCTRL,             // Auxiliary control
+  output wire       SPI0,                // Shield0 SPI enable
+  output wire       SPI1,                // Shield1 SPI enable
+  output wire       I2C0,                // Shield0 I2C enable
+  output wire       I2C1,                // Shield1 I2C enable
+  output wire       UART0,               // Shield0 UART enable
+  output wire       UART1);              // Shield1 UART enable
+
+  reg [8:0]        rx_shift_reg;
+  wire[8:0]        nxt_rx_shift;
+  reg [6:0]        string_length;
+  reg [7:0]        tube_string [127:0];
+  reg [7:0]        text_char;
+  integer          i;
+  reg              nxt_end_simulation;
+  reg              reg_end_simulation;
+  wire             char_received;
+  reg              reg_esc_code_mode;  // Escape code mode
+  reg              reg_aux_ctrl_mode;  // Auxiliary control capture mode
+  reg [7:0]        reg_aux_ctrl;       // Registered Auxiliary control
+  reg              reg_dbgtester_enable;
+  reg              SPI0_reg;
+  reg              SPI1_reg;
+  reg              I2C0_reg;
+  reg              I2C1_reg;
+  reg              UART0_reg;
+  reg              UART1_reg;
+
+  // Receive shift register
+  assign nxt_rx_shift  = {RXD,rx_shift_reg[8:1]};
+  assign char_received = (rx_shift_reg[0]==1'b0);
+
+  initial
+  begin
+  SPI0_reg  <= 1'b0;
+  SPI1_reg  <= 1'b0;
+  I2C0_reg  <= 1'b0;
+  I2C1_reg  <= 1'b0;
+  UART0_reg <= 1'b0;
+  UART1_reg <= 1'b0;
+  end
+
+
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      rx_shift_reg <= {9{1'b1}};
+    else
+      if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+        rx_shift_reg <= {9{1'b1}};
+      else
+        rx_shift_reg <= nxt_rx_shift;
+  end
+
+  // Escape code mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_esc_code_mode <= 1'b0;
+    else // Set to escape mode if ESC code is detected
+      if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+        reg_esc_code_mode <= 1'b1;
+      else if (char_received)
+        reg_esc_code_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl_mode <= 1'b0;
+    else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+        reg_aux_ctrl_mode <= 1'b1;
+      else if (char_received)
+        reg_aux_ctrl_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture data register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl <= {8{1'b0}};
+    else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+      if (char_received & (reg_aux_ctrl_mode==1'b1))
+        reg_aux_ctrl <= rx_shift_reg[8:1];
+  end
+
+  assign AUXCTRL = reg_aux_ctrl;
+
+  // Debug tester enable
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_dbgtester_enable <= 1'b0;
+    else // Enable debug tester if ESC-0x11 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+        reg_dbgtester_enable <= 1'b1;
+      else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+        // Disable debug tester if ESC-0x12 sequence is detected
+        reg_dbgtester_enable <= 1'b0;
+  end
+
+  assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+  // Message display
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_tube
+  if (~RESETn)
+    begin
+    string_length = 7'b0;
+    nxt_end_simulation <= 1'b0;
+     for (i=0; i<= 127; i=i+1) begin
+       tube_string [i] = 8'h00;
+     end
+    end
+  else
+    if (char_received)
+        begin
+        if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+          begin
+          // Escape code, or in escape code mode
+          // Data receive can be command, aux ctrl data
+          // Ignore this data
+          end
+        else if  (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+          nxt_end_simulation <= 1'b1;
+        else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+          // New line
+          begin
+          tube_string[string_length] = 8'h00;
+          $write("%t UART: ",$time);
+
+          for (i=0; i<= string_length; i=i+1)
+            begin
+            text_char = tube_string[i];
+            $write("%s",text_char);
+            end
+
+          $write("\n");
+          string_length = 7'b0;
+          end
+        else if  (rx_shift_reg[8:1]==8'h0F)
+          begin
+          $write("%t UART: Switching on Shield I2C, SPI and UART\n",$time);
+            SPI0_reg  <= 1'b1;
+       SPI1_reg  <= 1'b1;
+       I2C0_reg  <= 1'b1;
+       I2C1_reg  <= 1'b1;
+       UART0_reg <= 1'b1;
+            UART1_reg <= 1'b1;
+          end
+
+        else
+          begin
+          tube_string[string_length] = rx_shift_reg[8:1];
+          string_length = string_length + 1;
+          if (string_length >79) // line too long, display and clear buffer
+            begin
+            tube_string[string_length] = 8'h00;
+            $write("%t UART: ",$time);
+
+            for (i=0; i<= string_length; i=i+1)
+              begin
+              text_char = tube_string[i];
+              $write("%s",text_char);
+              end
+
+            $write("\n");
+            string_length = 7'b0;
+
+            end
+
+          end
+
+        end
+
+  end // p_TUBE
+
+  // Delay for simulation end
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_sim_end
+  if (~RESETn)
+    begin
+    reg_end_simulation <= 1'b0;
+    end
+  else
+    reg_end_simulation  <= nxt_end_simulation;
+    if (reg_end_simulation==1'b1)
+      begin
+      $write("%t UART: Test Ended\n",$time);
+      $stop;
+      end
+
+  end
+
+  assign SIMULATIONEND = nxt_end_simulation & ~reg_end_simulation;
+
+  assign SPI0  = SPI0_reg;
+  assign SPI1  = SPI1_reg;
+  assign I2C0  = I2C0_reg;
+  assign I2C1  = I2C1_reg;
+  assign UART0 = UART0_reg;
+  assign UART1 = UART1_reg;
+
+endmodule

ssp_tx/sim/func001/debussy.bat

@@ -0,0 +1,27 @@
+::关闭回显 
+@ECHO OFF 
+::设置软件路径 
+SET Debussy=C:\Novas\Debussy\bin\Debussy.exe
+SET vericom=C:\Novas\Debussy\bin\vericom.exe
+SET vhdlcom=C:\Novas\Debussy\bin\vhdlcom.exe
+
+::===== import design from file (compile design into ram) =====
+::仅适用于纯 v/sv 工程
+%Debussy% -sv -f ../file_ver.f
+
+::===== import design from library (compile design into library) =====
+::适用于 混合语言工程 和 纯 v/sv 工程
+::%vericom% -sv -2001 -f file_ver.f
+::%vhdlcom% -2000 -f file_vhd.f
+::%Debussy% -lib work -top top &
+
+::删除波形文件 
+::DEL Debussy.fsdb /q 
+
+::删除Debussy生成的相关文件 
+RD Debussy.exeLog  /s /q 
+DEL novas.rc /q 
+
+::退出命令行 
+EXIT
+

ssp_tx/sim/func001/find_unreferenced_sources.tcl

@@ -0,0 +1,143 @@
+#usage : do find_unreferenced_sources.tcl [-d]
+# if -d is not specified,only list out the unrefferenced files
+# the script does:
+# step 1 :generate the report
+# step 2 :get all referced files from the report
+# step 3 :get all compiled files from the 01_source/01_func directory
+# step 4 :compare the two list,find out the unrefferenced ones
+# step 5:optionnnaly,delete the unrefferenced files
+# step 6: remove the generated reports
+
+proc relative_to_absolute {relative_path} {
+
+    #replace all "../" and count how many "../" occured in the original string
+    set parent_dir_count [regsub -all {\.\.\/} $relative_path "" sufix_path];
+    set redir_path [pwd];
+
+    #cut the current path by N-times to get the common parent path for both "abs" and "rela" 
+    for {set i 0 } {$i < $parent_dir_count} {incr i} {
+        set last_dir [file tail $redir_path];
+        regsub /$last_dir $redir_path "" redir_path;
+    }
+    set prefix_path $redir_path;
+#   puts redir_path=$redir_path
+    set absolute_path $prefix_path/$sufix_path;
+
+    return $absolute_path;
+}
+
+
+proc find_files  {root_path } {
+    set results [list];
+#   lappend results;
+
+    #store the current path
+    set current_path [pwd];
+    cd $root_path;
+    set root_path [pwd];
+
+    puts "entering $root_path"
+    # get all files recusively
+    foreach element [glob -nocomplain *  ;] {
+
+    # entering sub dirs
+        if { [file isdirectory $element]} {
+
+            set sublist [find_files $element];
+            set results [concat $results $sublist];
+        } else {
+#            only valid source files are filtered
+            if {[string match "*.v" $element] || [string match "*.sv" $element] || [string match "*.vhd" $element] || [string match "*.vhdl" $element]} {
+                lappend results  "$root_path/$element";
+            }
+        }
+    }
+
+    cd $current_path;
+
+    puts "++++++++++++++++++++++++++++"
+    return $results;
+}
+
+.main clear
+#exit simulation ,unless the change dir will not work
+q -sim 
+
+puts "---------------------------------ATTENTION----------------------------------------"
+puts "----------- this file should be sourced after the vsim load sucessfully-----------"
+puts "----------- this file should be sourced from the funcXXX director-----------------"
+puts ""
+
+
+puts ":::::::::get referced dut files:::::::::"
+set referenced_files [list ]
+set f_report [open $TEMP_REF_FILES r];
+
+#read the report,get all referenced files
+while {![eof $f_report]} {
+    gets $f_report line ;
+
+    if { [string match  "*Source File*" $line] } {
+        lappend referenced_files $line;
+    }
+}
+close $f_report
+
+#remove those source file,point to precompiled vendor library
+#convert the relative path to absolute path
+#list referenced_dut_files;
+foreach element $referenced_files {
+    if { [string match  "*Source File: \.\./\.\./*" $element] } {
+        regsub {^.*Source File:} $element "" path;
+        set relative_path [string trim $path ];
+        set abs_path [relative_to_absolute $relative_path];
+        lappend referenced_dut_files $abs_path
+#       puts $abs_path
+    }
+}
+
+puts ":::::::::get all compiled source  files:::::::::"
+#get all source files in the source file directory ,recursively
+set root_path ../../../01_source/01_func;
+set all_sources [find_files $root_path;];
+.main clear
+
+puts ":::::::::try to match:::::::::"
+#try to match the two lists,and filter the mis-matched ones
+
+#set f_referenced_dut_files [open "referenced.txt" w+];
+#foreach sim_file $referenced_dut_files {
+#    puts $f_referenced_dut_files $sim_file;
+#}
+#close $f_referenced_dut_files;
+
+#set f_dir_files [open "dir.txt" w+];
+#foreach dir_file $all_sources {
+#    puts $f_dir_files $dir_file;
+#}
+#close $f_dir_files
+
+puts "found dismated files as follow:"
+set mis_matched_dir_files [list]
+foreach dir_file $all_sources {
+
+    set index [lsearch $referenced_dut_files $dir_file];
+    if {$index == -1} {
+        lappend mis_matched_dir_files $dir_file;
+        puts "path=$dir_file"
+    }
+}
+
+#if specified the -d switch,just delete the files
+if {$argc == 1 && [string equal $1 "-d"]} {
+
+    puts "the -d switch specified ,delete the dismatched files automatically"
+    foreach del_file $mis_matched_dir_files {
+        file delete -force $del_file 
+    }
+}
+
+
+#file delete -force $TEMP_REF_FILES
+
+

ssp_tx/sim/func001/format_save.tcl

@@ -0,0 +1,98 @@
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {true} {
+    # raw script code in pre_format
+    set pre_format {
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+}
+}; list
+# from stackoverflow.com "how to keep commands quiet in TCL?"
+# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
+# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
+# for instance: set a [open "giri.txt" r]; list
+
+if {true} {
+    # raw script code in post_format
+    set post_format {
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+}
+}; list
+
+# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
+if {true} {
+    # save current wave format to a tmp file
+    catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
+
+    if {$argc>=1} { # example: do savewave.tcl wave_name
+        set wave_name $1
+        if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
+            # replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
+            while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
+                regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
+            }
+        } elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
+            # nop
+        } else {
+            echo "Invalid file name $wave_name!"
+            return
+        }
+        set fd_wave [open $wave_name.tcl w]
+        echo "Wave format saved to $wave_name.tcl"
+    } else { # example: do savewave.tcl
+        set fd_wave [open lastwave.tcl w]
+        echo "Wave format saved to lastwave.tcl"
+    }
+
+    set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
+
+    # put lines in pre_format to final file(the file specified in argument $1)
+    set lines [split $pre_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in tmp file to final file(the file specified in argument $1)
+    while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
+        if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
+            # if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
+            regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
+            # and then add eval in the biginning
+            regsub (^) $wave_format_line {eval } wave_format_line
+        }
+        # make virtual signal ok
+        if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
+            regsub -all {\{} $wave_format_line {[subst &} wave_format_line
+            regsub -all {\}} $wave_format_line {&]} wave_format_line
+        }
+        regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in post_format to final file(the file specified in argument $1)
+    set lines [split $post_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    close $fd_wave
+    close $fd_intermediate_wave_format_file
+}

ssp_tx/sim/func001/lastwave.tcl

@@ -0,0 +1,280 @@
+
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/read_agent_state
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mode
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/write_ping_n_or_pong
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ping_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_pong_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en_d1
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_start
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_mode
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_next_page
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/tmr_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/page_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_lo_addr
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_grant
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req_end
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_addr
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_req
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_data
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_done
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/fifo_latency_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_dq
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_full
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_empty
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_rd
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/state_c
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_m_write_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_read_page_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_type
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_ack
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_type
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_ack
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_waddr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_re
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata_vld
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_pending
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_writing
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_pending
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_reading
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mr_f
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mw_f
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_m_r
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_grant
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req_end
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_op_addr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/cnt_read_page_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_1
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_2
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_3
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_die
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_block
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_col_r
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_we
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_re
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_data_out
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_full
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_empty
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_q
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req_end
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/o_grant
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/state_c
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/stat_vld
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/status
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/init_done
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/done
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/block_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/state_c
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_full
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_low
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_high
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_2
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_3
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/wram_re_reg
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/read_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/write_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_data_out
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_out_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata_vld
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_we
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_add_byte
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_re_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_we_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/activate
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_in
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_row
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_col
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/status
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/busy
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/stat_vld
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_mram_area
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/ARBT_ADC_CS
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req_end
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_arbt_grant
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_op_addr
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_data
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_wr_done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_rd_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_data
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_smp_num
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_mram_data_volume
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_mram_area
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/NAND_WR_CS
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/ri_mode_code
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_axis
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_sensor
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req_end
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_arbt_grant
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_addr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_req
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_data
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_done
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_smp_num
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_data_volume
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_if_dpram_rd_done
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_addr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_data
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_done
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/vote_state
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ready
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ping_n_or_pong
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_clear
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_type
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/tmr_cnt
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/page_cnt
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_lo_addr
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req_end
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_grant
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_addr
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_data
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_done
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/burst_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/trunk_over
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/SCI_CS
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_trunk_id_cnt
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_type
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_ready
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_service_request
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/ccsds
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_active
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_cs
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_en
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_addr
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm_done
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci_done
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_burst_req
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_trunk_over
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_addr_offset
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_frame_cnt
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_din_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_cs_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_r_wn_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_din_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_cs_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_r_wn_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_addr_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/chksum
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/sensor_id
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/CS
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_ce_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_oe_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_we_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_addr
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/io_bank_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_op_addr
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_req
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_wr_done
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_rd_req
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_done
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/DIST_CS
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_1553_int_n
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_buf_service_request
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/w_buf_service_request
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/vector_word
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_mem_reg_n
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/r_1553_int_n_neg
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_op_addr
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_req
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_data
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_wr_done
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_rd_req
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_data
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_done
+eval TreeUpdate \[SetDefaultTree\]
+WaveRestoreCursors {{Cursor 1} {703840517004 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 248
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1575 ms}
+
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+

ssp_tx/sim/func001/run.tcl

@@ -0,0 +1,227 @@
+#quit -sim
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#unbound the the "work" lib dir from vsim,to remove it
+
+#when error do not save wave list
+if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
+    source savewave.tcl
+}
+#catch {q -sim} res
+#dataset close -all
+
+echo on
+.main clear
+
+puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
+
+vmap std $SIM_TOOL_PATH/std  ;
+vmap ieee $SIM_TOOL_PATH/ieee   ;
+
+set FUNC_SOURCE_DIR   ../../../01_source/01_func
+set TIMING_SOURCE_DIR ../../../01_source/02_timing
+
+set source_vhdl false
+set source_verilog false
+
+set LIB_OPTION ""
+set LOG_OPTION ""
+
+#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
+#    #-----------actel----------
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    if {[string equal -nocase vhd $TOP_FILE_LANG]} {
+#        vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
+#    } else {
+#        vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
+#    }
+#    set LIB_OPTION "-L ${ACTEL_FAMILY}"
+#
+#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#        set source_vhdl true
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
+#        set source_verilog true
+#    }
+#    if { [string equal -nocase true $source_vhdl] } {
+#        #-----------xilinx vhdl----------
+#        #puts "vhdl file exist!"
+#        vmap simprim       $VHDL_LIB/simprim
+#        vmap unisim        $VHDL_LIB/unisim
+#        vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
+#        vmap unimacro      $VHDL_LIB/unimacro
+#        set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
+#    }
+#
+#    if { [string equal -nocase true $source_verilog] } {
+#        #-----------xilinx verilog----------
+#        #puts "verilog file exist!"
+#        vmap unisims_ver       $VLOG_LIB/unisims_ver
+#        vmap simprims_ver      $VLOG_LIB/simprims_ver
+#        vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
+#        vmap unimacro_ver      $VLOG_LIB/unimacro_ver
+#        vmap secureip          $VLOG_LIB/secureip
+#        set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
+#    }
+#}
+
+set defs [dict create;] ;
+dict append defs CASE_NAME $CASE_NAME;
+dict append defs TOP_ENTITY $TOP_ENTITY;
+dict append defs TOP_INSTANCE $TOP_INSTANCE;
+dict append defs timing;
+dict append defs SIM_TIME $SIM_TIME ;
+
+set def_string "";
+dict for {def_name def_value} $defs {
+    set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
+}
+puts "the define string is:$def_string"
+
+
+#file delete -force work            ;
+
+vlib $WORK_LIB_DIR/${CASE_DIR};
+vmap work $WORK_LIB_DIR/${CASE_DIR};
+catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock        } res;
+catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/     } res;
+
+#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
+#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
+
+#if {[info exists 1]} {
+#    set SIM_TIME $1
+#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
+
+
+
+#by default,all cases use the same source file list
+set VLOG_SOURCE_LIST ../file_ver.f;
+set VHDL_SOURCE_LIST ../file_vhd.f;
+
+#we specify individual file list for single case
+if {[file exists file_ver.f ]} {
+    puts "---->using case dependent verilog file list"
+    set VLOG_SOURCE_LIST file_ver.f;
+}
+
+if {[file exists file_vhd.f ]} {
+    puts "---->using case dependent vhdl file list"
+    set VHDL_SOURCE_LIST file_vhd.f;
+}
+
+if {![string equal vhd $TOP_FILE_LANG]} {
+    set GLBL glbl
+}
+
+if {$SIM_TYPE == "timing"} {
+
+        set SDF_TYPE "-sdfmax";
+        set SDFCOM_TYPE "-maxdelays";
+
+    puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
+        if {[string equal $CORNER_TYPE "01_min" ]} {
+                set SDF_TYPE "-sdfmin";
+                set SDFCOM_TYPE "-mindelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "02_type" ]} {
+                set SDF_TYPE "-sdftyp";
+                set SDFCOM_TYPE "-typdelays";
+                puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "03_max" ]} {
+                set SDF_TYPE "-sdfmax";
+                set SDFCOM_TYPE "-maxdelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
+        }
+        
+        if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
+                puts "++++++++++ develop kit is libero ++++++++++";
+        } else {
+                puts "++++++++++ develop kit is not libero ++++++++++";
+                set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
+        }
+        
+        sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
+
+        #in timing simulation ,here only glbl may be compiled seperately
+    if {[file exists  ${VLOG_SOURCE_LIST}]} {
+        vlog  -incr -quiet  -sv  +cover=${COVERAGE_OPTION}  +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
+    }
+
+    vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
+
+    vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
+
+    eval vopt  ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
+        +initmem+0 +initreg+0 +initwire+0;
+
+
+    eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout  \
+    +no_notifier +no_tchk_msg\
+    work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
+        ${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
+
+    do ../suppresswarning.tcl
+
+
+    catch {run ${SIM_TIME} } res
+} else {
+
+
+#compile source files
+    if {[file exists ${VLOG_SOURCE_LIST}]} {
+        puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
+#       vlog -incr -quiet   +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+        vlog  -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+    }
+
+
+    if {[file exists ${VHDL_SOURCE_LIST}]} {
+        puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
+        vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
+    }
+
+#        eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
+#        +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
+#            +initmem+0 +initreg+0 +initwire+0 \
+#            -suppress 2912 \
+#            -suppress 1127
+
+    #to mask 211 error
+    catch {
+                if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
+                                eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
+                                        -t 1ps -wlfopt -wlfcompress -nostdout  \
+                                        +initmem+0 +initreg+0 +initwire+0 \
+                                        +no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
+                                        -classdebug \
+                                        glbl work.${CASE_NAME} \
+                                        -wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
+                } else {
+                        restart -f
+                }
+        } res;
+
+    do ../suppresswarning.tcl
+
+    catch {do wave.tcl} res
+
+    set TEMP_REF_FILES info.txt;
+    write report -l $TEMP_REF_FILES
+
+    catch {run ${SIM_TIME} } res
+
+    do ../saveucdb.tcl
+#}
+
+set current_path [pwd]
+puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"

ssp_tx/sim/func001/runone.tcl

@@ -0,0 +1,20 @@
+quit -sim
+cd ..
+
+#clear the simulator transcript window and make the wave,data & coverage director
+.main clear
+
+set wrap_args [list];
+#put the do command $1-$9 to list,because we can't use the argv,we should construct the "argv" mannully.
+for {set i 1} {$i <= $argc} {incr i 1} {
+    lappend wrap_args [set $i];
+}
+
+#echo $args
+
+eval do runone.tcl $wrap_args
+
+
+
+
+

ssp_tx/sim/func001/save.tcl

@@ -0,0 +1,7 @@
+if {$argc>=1} {
+    catch {write format wave -window Wave $1.tcl} res
+} else {
+    catch {write format wave -window Wave case.tcl} res
+}
+
+

ssp_tx/sim/func001/savewave.tcl

@@ -0,0 +1,114 @@
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {true} {
+    # raw script code in pre_format
+    set pre_format {
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+}
+}; list
+# from stackoverflow.com "how to keep commands quiet in TCL?"
+# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
+# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
+# for instance: set a [open "giri.txt" r]; list
+
+if {true} {
+    # raw script code in post_format
+    set post_format {
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+}
+}; list
+
+# support save format when only open .wlf instead of run a case
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+
+# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
+if {true} {
+    # save current wave format to a tmp file
+    catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
+
+    if {$argc>=1} { # example: do savewave.tcl wave_name
+        set wave_name $1
+        if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
+            # replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
+            while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
+                regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
+            }
+        } elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
+            # nop
+        } else {
+            echo "Invalid file name $wave_name!"
+            return
+        }
+        set fd_wave [open $wave_name.tcl w]
+        echo "Wave format saved to $wave_name.tcl"
+    } else { # example: do savewave.tcl
+        set fd_wave [open wave1.tcl w]
+        echo "Wave format saved to wave1.tcl"
+    }
+
+    set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
+
+    # put lines in pre_format to final file(the file specified in argument $1)
+    set lines [split $pre_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in tmp file to final file(the file specified in argument $1)
+    while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
+        if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
+            # if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
+            regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
+            # and then add eval in the biginning
+            regsub (^) $wave_format_line {eval } wave_format_line
+        }
+        # make virtual signal ok
+        if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
+            regsub -all {\{} $wave_format_line {[subst &} wave_format_line
+            regsub -all {\}} $wave_format_line {&]} wave_format_line
+        }
+        regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in post_format to final file(the file specified in argument $1)
+    set lines [split $post_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    close $fd_wave
+    close $fd_intermediate_wave_format_file
+}

ssp_tx/sim/func001/tb.sv

@@ -0,0 +1,73 @@
+`timescale 1ns/1ps
+
+module
+    `CASE_NAME();
+    `include "../instantiate_top.sv"
+	
+	final mti_fli::mti_Cmd("do ../saveucdb.tcl");
+
+    initial begin
+      $fsdbDumpfile("fsdb_wave.fsdb");
+      $fsdbDumpvars;
+    end
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+/*to end the simulation commandary*/
+/*if you want to end the simulation case by case,just comment the line
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
+//TODO:
+
+
+    logic [7:0]  ssp_rx_tdata;
+    logic        ssp_rx_tvalid;
+    logic        ssp_rx_tready = 0;
+    logic [31:0] error_status;
+
+    // instance vip
+    vip_clock # (.FREQUENCY_MHZ(100)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
+    
+    vip_clock # (.FREQUENCY_MHZ(110)) u1_clock(.duty_percent(50), .jitter_percent(0), .clk(ssp_rx_clk));
+
+    ssp_rx # (
+        .FREQ_HZ(110e6),
+        .SSP_HZ(10e6)
+    ) u_ssp_rx (
+        .clk        (ssp_rx_clk),
+        .aresetn    (aresetn),
+
+        .tdata      (ssp_rx_tdata),
+        .tvalid     (ssp_rx_tvalid),
+        .tready     (ssp_rx_tready),
+
+        .ssp_clk    (ssp_clk),
+        .ssp_csn    (ssp_csn),
+        .ssp_data   (ssp_data),
+
+        .error_status (error_status)
+    );
+
+    initial begin
+        aresetn = 1'b0;
+        #200ns;
+        aresetn = 1'b1;
+    end
+
+    initial begin
+        tdata  = 8'h00;
+        tvalid = 1'b0;
+        wait (!aresetn);
+        #100ns;
+
+        repeat (20) begin
+            // send a byte
+            tvalid = 1'b1;
+            @(posedge tready) #1ns;
+            tvalid = 1'b0;
+            tdata++;
+        end
+
+        //$finish;
+    end
+
+		
+endmodule

ssp_tx/sim/func001/vip_clock.sv

@@ -0,0 +1,29 @@
+module vip_clock
+    #(
+    parameter FREQUENCY_MHZ = 1,
+    parameter PHASE_DEGREE = 0
+    )
+    (
+    input int duty_percent = 50,//dynamical parameter
+    input int jitter_percent = 0,//dynamical parameter
+    output clk
+    );
+
+
+
+logic ideal_clk;
+
+initial begin
+    ideal_clk = 0;
+    #(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
+    forever begin
+        ideal_clk = 0;
+        #(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);
+
+        ideal_clk = 1;
+        #(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
+    end
+end
+
+assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk =  ideal_clk;
+endmodule

ssp_tx/sim/func001/wave.tcl

@@ -0,0 +1,75 @@
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+#preset envieroment variables
+if {[info exists SIM_TYPE] && $SIM_TYPE == "timing"} {
+    
+} else {
+
+    puts "---->checing the simulator status to decide whether to restore the wave session.................."
+    puts "---->the runstatus is :[runStatus]"
+    #if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "error" ]} {
+        puts "---->trying  restore to saved wave window.................."
+
+        catch {
+            set size [file size lastwave.tcl];
+            #check if size is too much
+            if($size > (10*1024){
+                puts "lastwave.tcl size is $size,try to recover"
+                do lastwave.tcl
+            }
+        } res;
+    #} 
+
+     
+    # catch {log -mvcreccomplete -r -depth 6  /* } res 
+    
+    catch {log -mvcreccomplete -r -depth 6  /$CASE_NAME/*} res 
+    catch {log -mvcreccomplete -r -depth 6  /$CASE_NAME/$TOP_INSTANCE/*} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/CENTRAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/TRAIN_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/SEQUENCER_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/GENIMGVAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRXDATA_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_AREF_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_INIT_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_READ_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_WRITE_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instLow} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_FRMRDCTRL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGTX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGSPI_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/COMMANDHANDLER_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/ERUPRAMCAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/ERUPSUM_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/FRMHEADWR_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/GUIDEPIEZORX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/STATE_RETURN_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TEMP461_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIMEPRO_inst} res 
+	
+	
+	
+#   log -class pkg_uart::uart
+#   catch {class/pkg_uart::uart::uart__2} res;
+}