首次提交

2026-03-06 16:22:17 +08:00
commit b8fe9f77ec
465 changed files with 115939 additions and 0 deletions
--- a/ssp_tx/sim/_file_vhd.f
+++ b/ssp_tx/sim/_file_vhd.f
@@ -0,0 +1,8 @@
+#../../../01_source/01_func/IP/*.vhd
+../../../01_source/01_func/SRC/ad_da_pack.vhd
+../../../01_source/01_func/SRC/com_pack.vhd
+../../../01_source/01_func/SRC/ld_pack.vhd
+../../../01_source/01_func/SRC/top_pack.vhd
+
+../../../01_source/01_func/IP/*.vhd
+../../../01_source/01_func/SRC/*.vhd
--- a/ssp_tx/sim/clear.tcl
+++ b/ssp_tx/sim/clear.tcl
@@ -0,0 +1,23 @@
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+echo on
+
+#quit from current runing simulation
+quit -sim
+#clear the transcript window,only valid in batch mode
+
+if [batch_mode] {
+#   log /*
+} else {
+    .main clear
+}
--- a/ssp_tx/sim/commit.cmd
+++ b/ssp_tx/sim/commit.cmd
@@ -0,0 +1,28 @@
+svn add . data --depth=empty
+svn add . data/*.txt data/*.m
+
+svn add . coverage --depth=empty
+svn add . coverage/*.ucdb
+
+svn add . func* --depth=empty
+rem walk through all func* director
+for /D  %%i in (fun*) do  (
+svn add . %%i/*.sv 
+svn add . %%i/*.tcl 
+svn add . %%i/*.do 
+svn add . %%i/*.mif )
+
+
+svn add . timing* --depth=empty
+rem walk through all func* director
+for /D  %%i in (timing*) do  (
+svn add . %%i/*.sv 
+svn add . %%i/*.tcl 
+svn add . %%i/*.do 
+svn add . %%i/*.mif )
+
+svn add --depth=empty  . *.tcl *.sv *.v *.bat *.cmd *.f *.do
+
+svn status -v .
+svn commit -m "autocommit" .
+        pause
--- a/ssp_tx/sim/file_ver.f
+++ b/ssp_tx/sim/file_ver.f
@@ -0,0 +1,6 @@
+define+__MICROSATE_SIM__
+vip_clock.sv
+tb.sv
+../glbl.v
+../../src/ssp_tx.sv
+../../../ssp_rx/src/ssp_rx.sv
--- a/ssp_tx/sim/find_unreferenced_sources.tcl
+++ b/ssp_tx/sim/find_unreferenced_sources.tcl
@@ -0,0 +1,119 @@
+
+proc relative_to_absolute {relative_path} {
+
+    #replace all "../" and count how many "../" occured in the original string
+    set parent_dir_count [regsub -all {\.\.\/} $relative_path "" sufix_path]
+    set redir_path [pwd];
+
+    #cut the current path by N-times to get the common parent path for both "abs" and "rela" 
+    for {set i 0 } {$i < $parent_dir_count} {incr i} {
+        set last_dir [file tail redir_path];
+        regsub /$last_dir $redir_path "" redir_path;
+    }
+    set prefix_path $redir_path;
+
+    set absolute_path $prefix_path/$sufix_path;
+
+    return $absolute_path;
+    
+}
+
+
+proc find_files  {root_path } {
+    list results;
+
+    #store the current path
+    set current_path [pwd];
+    cd $root_path;
+    set root_path [pwd];
+
+    puts "entering $root_path"
+    # get all files recusively
+    foreach element [glob -nocomplain *] {
+
+        # entering sub dirs
+        if { [file isdirectory $element]} {
+
+            set subList  [find_files $element];
+            set results [concat $results $subList];
+        } else {
+#            only valid source files are filtered
+            if {[string match "*.v" $element] || [string match "*.sv" $element] || [string match "*.vhd" $element] || [string match "*.vhdl" $element]} {
+                lappend results  "$root_path/$element";
+            }
+        }
+    }
+
+    cd $current_path;
+
+    return $results;
+}
+
+puts "---------------------------------ATTENTION----------------------------------------"
+puts "----------- this file should be sourced after the vsim load sucessfully-----------"
+puts "----------- this file should be sourced from the funcXXX director-----------------"
+puts ""
+
+#write report -l info.txt
+
+
+
+puts ":::::::::get referced dut files:::::::::"
+set f_report [open info.txt r];
+
+#read the report,get all referenced files
+while {![eof $f_report]} {
+    gets $f_report line 
+
+    if { [string match  "*Source File*" $line] } {
+        lappend referenced_files $line
+    }
+}
+close $f_report
+
+#remove those source file,point to precompiled vendor library
+#convert the relative path to absolute path
+list referenced_dut_files;
+foreach element $referenced_files {
+    if { [string match  "*Source File: \.\./\.\./*" $element] } {
+        regsub {^.*Source File:} $element "" path
+        set relative_path [string trim $path ]
+        set abs_path [relative_to_absolute $relative_path]
+        lappend referenced_dut_files $abs_path
+#       puts $abs_path
+    }
+}
+
+puts ":::::::::get all compiled source  files:::::::::"
+#get all source files in the source file directory ,recursively
+set root_path ../../../01_source/01_func;
+set all_sources [find_files $root_path ];
+
+puts ":::::::::try to match:::::::::"
+#try to match the two lists,and filter the mis-matched ones
+
+set f_referenced_dut_files [open "referenced.txt" w+];
+foreach sim_file $referenced_dut_files {
+    puts $f_referenced_dut_files $sim_file;
+}
+close $f_referenced_dut_files
+
+set f_dir_files [open "dir.txt" w+];
+foreach dir_file $all_sources {
+    puts $f_dir_files $dir_file;
+}
+close $f_dir_files
+
+lappend mis_matched_dir_files;
+foreach dir_file $all_sources {
+
+    puts $dir_file
+    set index [lsearch $referenced_dut_files $dir_file]
+    if {$index == -1} {
+        lappend mis_matched_dir_files $dir_file
+        puts dir=$dir_file
+    }
+}
+
+
+
--- a/ssp_tx/sim/func001/addwave.tcl
+++ b/ssp_tx/sim/func001/addwave.tcl
@@ -0,0 +1,21 @@
+echo off
+#useage do addwave.tcl uart,where uart is a module name
+#when there is mulitple matches,the 1st one is picked
+puts "---->find by design unit:$1"
+
+set patten  *$1*;
+#puts "---->find patten:$patten"
+
+set rslt [find instance -bydu $patten];
+#puts "---->find result:$rslt"
+
+regsub {\{} $rslt "" rslt;
+regsub {\}} $rslt "" rslt;
+
+regsub { (.*)} $rslt "" path;
+#puts "---->design path is:$path"
+
+set signal_list ${path}/*
+puts "---->list to be add to wave:$signal_list"
+
+add wave $signal_list
--- a/ssp_tx/sim/func001/can_transceiver.sv
+++ b/ssp_tx/sim/func001/can_transceiver.sv
@@ -0,0 +1,22 @@
+/*
+	can bus physical model by leguoqing
+*/
+
+module can_transceiver
+	(
+		output logic rxd = 1,
+		input  logic txd,
+		inout  tri1  line
+	);
+
+	always@(*)
+		if (line == 1'b0) rxd <= 1'b0;
+		else rxd <= 1'b1;
+
+	logic line_reg;
+	always@(*)
+		if (txd == 0) line_reg <= 0;
+		else line_reg <= 1;
+
+	assign line = line_reg ? 1'bz : 0;
+endmodule
--- a/ssp_tx/sim/func001/cmsdk_uart_capture_ard.v
+++ b/ssp_tx/sim/func001/cmsdk_uart_capture_ard.v
@@ -0,0 +1,254 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2010-2013 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2013-02-08 10:40:04 +0000 (Fri, 08 Feb 2013) $
+//
+//      Revision            : $Revision: 365823 $
+//
+//      Release Information : CM3DesignStart-r0p0-02rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK).  In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY    Capture XY to AUXCTRL output
+// ESC - 0x11         Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12         Clear DEBUG_TESTER_ENABLE to 0
+
+
+module cmsdk_uart_capture_ard (
+  input  wire       RESETn,              // Power on reset
+  input  wire       CLK,                 // Clock (baud rate)
+  input  wire       RXD,                 // Received data
+  output wire       SIMULATIONEND,       // Simulation end indicator
+  output wire       DEBUG_TESTER_ENABLE, // Enable debug tester
+  output wire [7:0] AUXCTRL,             // Auxiliary control
+  output wire       SPI0,                // Shield0 SPI enable
+  output wire       SPI1,                // Shield1 SPI enable
+  output wire       I2C0,                // Shield0 I2C enable
+  output wire       I2C1,                // Shield1 I2C enable
+  output wire       UART0,               // Shield0 UART enable
+  output wire       UART1);              // Shield1 UART enable
+
+  reg [8:0]        rx_shift_reg;
+  wire[8:0]        nxt_rx_shift;
+  reg [6:0]        string_length;
+  reg [7:0]        tube_string [127:0];
+  reg [7:0]        text_char;
+  integer          i;
+  reg              nxt_end_simulation;
+  reg              reg_end_simulation;
+  wire             char_received;
+  reg              reg_esc_code_mode;  // Escape code mode
+  reg              reg_aux_ctrl_mode;  // Auxiliary control capture mode
+  reg [7:0]        reg_aux_ctrl;       // Registered Auxiliary control
+  reg              reg_dbgtester_enable;
+  reg              SPI0_reg;
+  reg              SPI1_reg;
+  reg              I2C0_reg;
+  reg              I2C1_reg;
+  reg              UART0_reg;
+  reg              UART1_reg;
+
+  // Receive shift register
+  assign nxt_rx_shift  = {RXD,rx_shift_reg[8:1]};
+  assign char_received = (rx_shift_reg[0]==1'b0);
+
+  initial
+  begin
+  SPI0_reg  <= 1'b0;
+  SPI1_reg  <= 1'b0;
+  I2C0_reg  <= 1'b0;
+  I2C1_reg  <= 1'b0;
+  UART0_reg <= 1'b0;
+  UART1_reg <= 1'b0;
+  end
+
+
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      rx_shift_reg <= {9{1'b1}};
+    else
+      if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+        rx_shift_reg <= {9{1'b1}};
+      else
+        rx_shift_reg <= nxt_rx_shift;
+  end
+
+  // Escape code mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_esc_code_mode <= 1'b0;
+    else // Set to escape mode if ESC code is detected
+      if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+        reg_esc_code_mode <= 1'b1;
+      else if (char_received)
+        reg_esc_code_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl_mode <= 1'b0;
+    else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+        reg_aux_ctrl_mode <= 1'b1;
+      else if (char_received)
+        reg_aux_ctrl_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture data register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl <= {8{1'b0}};
+    else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+      if (char_received & (reg_aux_ctrl_mode==1'b1))
+        reg_aux_ctrl <= rx_shift_reg[8:1];
+  end
+
+  assign AUXCTRL = reg_aux_ctrl;
+
+  // Debug tester enable
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_dbgtester_enable <= 1'b0;
+    else // Enable debug tester if ESC-0x11 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+        reg_dbgtester_enable <= 1'b1;
+      else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+        // Disable debug tester if ESC-0x12 sequence is detected
+        reg_dbgtester_enable <= 1'b0;
+  end
+
+  assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+  // Message display
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_tube
+  if (~RESETn)
+    begin
+    string_length = 7'b0;
+    nxt_end_simulation <= 1'b0;
+     for (i=0; i<= 127; i=i+1) begin
+       tube_string [i] = 8'h00;
+     end
+    end
+  else
+    if (char_received)
+        begin
+        if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+          begin
+          // Escape code, or in escape code mode
+          // Data receive can be command, aux ctrl data
+          // Ignore this data
+          end
+        else if  (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+          nxt_end_simulation <= 1'b1;
+        else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+          // New line
+          begin
+          tube_string[string_length] = 8'h00;
+          $write("%t UART: ",$time);
+
+          for (i=0; i<= string_length; i=i+1)
+            begin
+            text_char = tube_string[i];
+            $write("%s",text_char);
+            end
+
+          $write("\n");
+          string_length = 7'b0;
+          end
+        else if  (rx_shift_reg[8:1]==8'h0F)
+          begin
+          $write("%t UART: Switching on Shield I2C, SPI and UART\n",$time);
+            SPI0_reg  <= 1'b1;
+       SPI1_reg  <= 1'b1;
+       I2C0_reg  <= 1'b1;
+       I2C1_reg  <= 1'b1;
+       UART0_reg <= 1'b1;
+            UART1_reg <= 1'b1;
+          end
+
+        else
+          begin
+          tube_string[string_length] = rx_shift_reg[8:1];
+          string_length = string_length + 1;
+          if (string_length >79) // line too long, display and clear buffer
+            begin
+            tube_string[string_length] = 8'h00;
+            $write("%t UART: ",$time);
+
+            for (i=0; i<= string_length; i=i+1)
+              begin
+              text_char = tube_string[i];
+              $write("%s",text_char);
+              end
+
+            $write("\n");
+            string_length = 7'b0;
+
+            end
+
+          end
+
+        end
+
+  end // p_TUBE
+
+  // Delay for simulation end
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_sim_end
+  if (~RESETn)
+    begin
+    reg_end_simulation <= 1'b0;
+    end
+  else
+    reg_end_simulation  <= nxt_end_simulation;
+    if (reg_end_simulation==1'b1)
+      begin
+      $write("%t UART: Test Ended\n",$time);
+      $stop;
+      end
+
+  end
+
+  assign SIMULATIONEND = nxt_end_simulation & ~reg_end_simulation;
+
+  assign SPI0  = SPI0_reg;
+  assign SPI1  = SPI1_reg;
+  assign I2C0  = I2C0_reg;
+  assign I2C1  = I2C1_reg;
+  assign UART0 = UART0_reg;
+  assign UART1 = UART1_reg;
+
+endmodule
--- a/ssp_tx/sim/func001/debussy.bat
+++ b/ssp_tx/sim/func001/debussy.bat
@@ -0,0 +1,27 @@
+::关闭回显 
+@ECHO OFF 
+::设置软件路径 
+SET Debussy=C:\Novas\Debussy\bin\Debussy.exe
+SET vericom=C:\Novas\Debussy\bin\vericom.exe
+SET vhdlcom=C:\Novas\Debussy\bin\vhdlcom.exe
+
+::===== import design from file (compile design into ram) =====
+::仅适用于纯 v/sv 工程
+%Debussy% -sv -f ../file_ver.f
+
+::===== import design from library (compile design into library) =====
+::适用于 混合语言工程 和 纯 v/sv 工程
+::%vericom% -sv -2001 -f file_ver.f
+::%vhdlcom% -2000 -f file_vhd.f
+::%Debussy% -lib work -top top &
+
+::删除波形文件 
+::DEL Debussy.fsdb /q 
+
+::删除Debussy生成的相关文件 
+RD Debussy.exeLog  /s /q 
+DEL novas.rc /q 
+
+::退出命令行 
+EXIT
+
--- a/ssp_tx/sim/func001/find_unreferenced_sources.tcl
+++ b/ssp_tx/sim/func001/find_unreferenced_sources.tcl
@@ -0,0 +1,143 @@
+#usage : do find_unreferenced_sources.tcl [-d]
+# if -d is not specified,only list out the unrefferenced files
+# the script does:
+# step 1 :generate the report
+# step 2 :get all referced files from the report
+# step 3 :get all compiled files from the 01_source/01_func directory
+# step 4 :compare the two list,find out the unrefferenced ones
+# step 5:optionnnaly,delete the unrefferenced files
+# step 6: remove the generated reports
+
+proc relative_to_absolute {relative_path} {
+
+    #replace all "../" and count how many "../" occured in the original string
+    set parent_dir_count [regsub -all {\.\.\/} $relative_path "" sufix_path];
+    set redir_path [pwd];
+
+    #cut the current path by N-times to get the common parent path for both "abs" and "rela" 
+    for {set i 0 } {$i < $parent_dir_count} {incr i} {
+        set last_dir [file tail $redir_path];
+        regsub /$last_dir $redir_path "" redir_path;
+    }
+    set prefix_path $redir_path;
+#   puts redir_path=$redir_path
+    set absolute_path $prefix_path/$sufix_path;
+
+    return $absolute_path;
+}
+
+
+proc find_files  {root_path } {
+    set results [list];
+#   lappend results;
+
+    #store the current path
+    set current_path [pwd];
+    cd $root_path;
+    set root_path [pwd];
+
+    puts "entering $root_path"
+    # get all files recusively
+    foreach element [glob -nocomplain *  ;] {
+
+    # entering sub dirs
+        if { [file isdirectory $element]} {
+
+            set sublist [find_files $element];
+            set results [concat $results $sublist];
+        } else {
+#            only valid source files are filtered
+            if {[string match "*.v" $element] || [string match "*.sv" $element] || [string match "*.vhd" $element] || [string match "*.vhdl" $element]} {
+                lappend results  "$root_path/$element";
+            }
+        }
+    }
+
+    cd $current_path;
+
+    puts "++++++++++++++++++++++++++++"
+    return $results;
+}
+
+.main clear
+#exit simulation ,unless the change dir will not work
+q -sim 
+
+puts "---------------------------------ATTENTION----------------------------------------"
+puts "----------- this file should be sourced after the vsim load sucessfully-----------"
+puts "----------- this file should be sourced from the funcXXX director-----------------"
+puts ""
+
+
+puts ":::::::::get referced dut files:::::::::"
+set referenced_files [list ]
+set f_report [open $TEMP_REF_FILES r];
+
+#read the report,get all referenced files
+while {![eof $f_report]} {
+    gets $f_report line ;
+
+    if { [string match  "*Source File*" $line] } {
+        lappend referenced_files $line;
+    }
+}
+close $f_report
+
+#remove those source file,point to precompiled vendor library
+#convert the relative path to absolute path
+#list referenced_dut_files;
+foreach element $referenced_files {
+    if { [string match  "*Source File: \.\./\.\./*" $element] } {
+        regsub {^.*Source File:} $element "" path;
+        set relative_path [string trim $path ];
+        set abs_path [relative_to_absolute $relative_path];
+        lappend referenced_dut_files $abs_path
+#       puts $abs_path
+    }
+}
+
+puts ":::::::::get all compiled source  files:::::::::"
+#get all source files in the source file directory ,recursively
+set root_path ../../../01_source/01_func;
+set all_sources [find_files $root_path;];
+.main clear
+
+puts ":::::::::try to match:::::::::"
+#try to match the two lists,and filter the mis-matched ones
+
+#set f_referenced_dut_files [open "referenced.txt" w+];
+#foreach sim_file $referenced_dut_files {
+#    puts $f_referenced_dut_files $sim_file;
+#}
+#close $f_referenced_dut_files;
+
+#set f_dir_files [open "dir.txt" w+];
+#foreach dir_file $all_sources {
+#    puts $f_dir_files $dir_file;
+#}
+#close $f_dir_files
+
+puts "found dismated files as follow:"
+set mis_matched_dir_files [list]
+foreach dir_file $all_sources {
+
+    set index [lsearch $referenced_dut_files $dir_file];
+    if {$index == -1} {
+        lappend mis_matched_dir_files $dir_file;
+        puts "path=$dir_file"
+    }
+}
+
+#if specified the -d switch,just delete the files
+if {$argc == 1 && [string equal $1 "-d"]} {
+
+    puts "the -d switch specified ,delete the dismatched files automatically"
+    foreach del_file $mis_matched_dir_files {
+        file delete -force $del_file 
+    }
+}
+
+
+#file delete -force $TEMP_REF_FILES
+
+
--- a/ssp_tx/sim/func001/format_save.tcl
+++ b/ssp_tx/sim/func001/format_save.tcl
@@ -0,0 +1,98 @@
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {true} {
+    # raw script code in pre_format
+    set pre_format {
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+}
+}; list
+# from stackoverflow.com "how to keep commands quiet in TCL?"
+# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
+# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
+# for instance: set a [open "giri.txt" r]; list
+
+if {true} {
+    # raw script code in post_format
+    set post_format {
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+}
+}; list
+
+# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
+if {true} {
+    # save current wave format to a tmp file
+    catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
+
+    if {$argc>=1} { # example: do savewave.tcl wave_name
+        set wave_name $1
+        if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
+            # replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
+            while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
+                regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
+            }
+        } elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
+            # nop
+        } else {
+            echo "Invalid file name $wave_name!"
+            return
+        }
+        set fd_wave [open $wave_name.tcl w]
+        echo "Wave format saved to $wave_name.tcl"
+    } else { # example: do savewave.tcl
+        set fd_wave [open lastwave.tcl w]
+        echo "Wave format saved to lastwave.tcl"
+    }
+
+    set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
+
+    # put lines in pre_format to final file(the file specified in argument $1)
+    set lines [split $pre_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in tmp file to final file(the file specified in argument $1)
+    while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
+        if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
+            # if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
+            regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
+            # and then add eval in the biginning
+            regsub (^) $wave_format_line {eval } wave_format_line
+        }
+        # make virtual signal ok
+        if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
+            regsub -all {\{} $wave_format_line {[subst &} wave_format_line
+            regsub -all {\}} $wave_format_line {&]} wave_format_line
+        }
+        regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in post_format to final file(the file specified in argument $1)
+    set lines [split $post_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    close $fd_wave
+    close $fd_intermediate_wave_format_file
+}
--- a/ssp_tx/sim/func001/lastwave.tcl
+++ b/ssp_tx/sim/func001/lastwave.tcl
@@ -0,0 +1,280 @@
+
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/read_agent_state
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mode
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/write_ping_n_or_pong
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_ping_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_pong_ready
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/agent_en_d1
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_start
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_mode
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_read_next_page
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/tmr_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/page_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/buf_lo_addr
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_grant
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_arb_req_end
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_addr
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_req
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_data
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/mram_wr_done
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/fifo_latency_cnt
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_dq
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_full
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_empty
+add wave -noupdate -expand -group nand_read_agent /$CASE_NAME/u0_hdtest01_top/inst_nand_read_agent/nand_fifo_rd
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/state_c
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_m_write_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/end_read_page_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_type
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_ack
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_type
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_ack
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_waddr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_wdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_re
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata_vld
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/program_buf_rdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_next_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/write_pending
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_writing
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/read_pending
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/is_reading
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mr_f
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/wait_mram_mw_f
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_m_r
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_grant
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_arb_req_end
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_op_addr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_wr_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_req
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rdata
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/mram_rd_done
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/cnt_read_page_tmr
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_1
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_2
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_nand_block_3
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_die
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_block
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/addr_page
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/add_col_r
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_we
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_re
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_data_out
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_full
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_empty
+add wave -noupdate -group nand_ctrl /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rfifo_q
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/i_req_end
+add wave -noupdate -group arbiter /$CASE_NAME/u0_hdtest01_top/u8_arbiter_wrap/o_grant
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/state_c
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/stat_vld
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/status
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/init_done
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/done
+add wave -noupdate -group marm_cfg /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/u_mram_cfg/block_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/state_c
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_full
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ale_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cle_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/re_n_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/we_n_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_en_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_low
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/ce_n_high
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_1
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_2
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_ctrl/rd_3
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/wram_re_reg
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/read_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/write_flag
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_data_out
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/dq_out_0
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata_vld
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/rfifo_we
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/program_buf_rdata
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_add_byte
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_re_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cnt_we_n
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/activate
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/cmd_in
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_row
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/add_col
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/status
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/busy
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/stat_vld
+add wave -noupdate -group nand_phy /$CASE_NAME/u0_hdtest01_top/inst_nand_top/u_nand_phy/done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_mram_area
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/ARBT_ADC_CS
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_arbt_req_end
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_arbt_grant
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_op_addr
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_wr_data
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_wr_done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_user_rd_req
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_data
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/i_user_rd_done
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/r_smp_num
+add wave -noupdate -group adc_write /$CASE_NAME/u0_hdtest01_top/u10_adc_arbiter_if_adaptor/o_mram_data_volume
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_mram_area
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/NAND_WR_CS
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/ri_mode_code
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_axis
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_sensor
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_arbt_req_end
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_arbt_grant
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_addr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_mram_rd_req
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_data
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_rd_done
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/r_smp_num
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_mram_data_volume
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/i_if_dpram_rd_done
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_addr
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_data
+add wave -noupdate -group nand_write /$CASE_NAME/u0_hdtest01_top/inst_nand_write_agent/o_if_dpram_wr_done
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/vote_state
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ready
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_ping_n_or_pong
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_clear
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_type
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/tmr_cnt
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/page_cnt
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/buf_lo_addr
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_req_end
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_arb_grant
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_addr
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_data
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/mram_rd_done
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/burst_req
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/trunk_over
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data
+add wave -noupdate -group vote /$CASE_NAME/u0_hdtest01_top/inst_data_tmr_vote/data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/SCI_CS
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_trunk_id_cnt
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_type
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/buf_ready
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_service_request
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/ccsds
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_active
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_cs
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_en
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_buf_rd_addr
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_buf_rd_data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_tm_done
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/update_sci_done
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/i_sci_data_vld
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_burst_req
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/o_sci_trunk_over
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_addr_offset
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_sci_frame_cnt
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_din_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_cs_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_wr_r_wn_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_din_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_cs_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_r_wn_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/r_dpram_addr_b
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/chksum
+add wave -noupdate -group sci_pkg /$CASE_NAME/u0_hdtest01_top/u99_test_eng_sci_data_pkg/sensor_id
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/CS
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_ce_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_oe_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_we_n
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_bank_addr
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/io_bank_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_op_addr
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_req
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_wr_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_wr_done
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/i_user_rd_req
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_data
+add wave -noupdate -group mram_driver /$CASE_NAME/u0_hdtest01_top/u9_mram_driver/o_user_rd_done
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/DIST_CS
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_1553_int_n
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_buf_service_request
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/w_buf_service_request
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/vector_word
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_mem_reg_n
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/r_1553_int_n_neg
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_op_addr
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_req
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_wr_data
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_wr_done
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/o_user_msg_rd_req
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_data
+add wave -noupdate -expand -group msg_dist /$CASE_NAME/u0_hdtest01_top/u1_bu65170_driver_top/u05_bu65170_msg_dist/i_user_msg_rd_done
+eval TreeUpdate \[SetDefaultTree\]
+WaveRestoreCursors {{Cursor 1} {703840517004 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 248
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1575 ms}
+
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+
--- a/ssp_tx/sim/func001/modelsim.ini
+++ b/ssp_tx/sim/func001/modelsim.ini
--- a/ssp_tx/sim/func001/run.tcl
+++ b/ssp_tx/sim/func001/run.tcl
@@ -0,0 +1,227 @@
+#quit -sim
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#unbound the the "work" lib dir from vsim,to remove it
+
+#when error do not save wave list
+if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
+    source savewave.tcl
+}
+#catch {q -sim} res
+#dataset close -all
+
+echo on
+.main clear
+
+puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
+
+vmap std $SIM_TOOL_PATH/std  ;
+vmap ieee $SIM_TOOL_PATH/ieee   ;
+
+set FUNC_SOURCE_DIR   ../../../01_source/01_func
+set TIMING_SOURCE_DIR ../../../01_source/02_timing
+
+set source_vhdl false
+set source_verilog false
+
+set LIB_OPTION ""
+set LOG_OPTION ""
+
+#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
+#    #-----------actel----------
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    if {[string equal -nocase vhd $TOP_FILE_LANG]} {
+#        vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
+#    } else {
+#        vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
+#    }
+#    set LIB_OPTION "-L ${ACTEL_FAMILY}"
+#
+#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#        set source_vhdl true
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
+#        set source_verilog true
+#    }
+#    if { [string equal -nocase true $source_vhdl] } {
+#        #-----------xilinx vhdl----------
+#        #puts "vhdl file exist!"
+#        vmap simprim       $VHDL_LIB/simprim
+#        vmap unisim        $VHDL_LIB/unisim
+#        vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
+#        vmap unimacro      $VHDL_LIB/unimacro
+#        set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
+#    }
+#
+#    if { [string equal -nocase true $source_verilog] } {
+#        #-----------xilinx verilog----------
+#        #puts "verilog file exist!"
+#        vmap unisims_ver       $VLOG_LIB/unisims_ver
+#        vmap simprims_ver      $VLOG_LIB/simprims_ver
+#        vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
+#        vmap unimacro_ver      $VLOG_LIB/unimacro_ver
+#        vmap secureip          $VLOG_LIB/secureip
+#        set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
+#    }
+#}
+
+set defs [dict create;] ;
+dict append defs CASE_NAME $CASE_NAME;
+dict append defs TOP_ENTITY $TOP_ENTITY;
+dict append defs TOP_INSTANCE $TOP_INSTANCE;
+dict append defs timing;
+dict append defs SIM_TIME $SIM_TIME ;
+
+set def_string "";
+dict for {def_name def_value} $defs {
+    set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
+}
+puts "the define string is:$def_string"
+
+
+#file delete -force work            ;
+
+vlib $WORK_LIB_DIR/${CASE_DIR};
+vmap work $WORK_LIB_DIR/${CASE_DIR};
+catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock        } res;
+catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/     } res;
+
+#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
+#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
+
+#if {[info exists 1]} {
+#    set SIM_TIME $1
+#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
+
+
+
+#by default,all cases use the same source file list
+set VLOG_SOURCE_LIST ../file_ver.f;
+set VHDL_SOURCE_LIST ../file_vhd.f;
+
+#we specify individual file list for single case
+if {[file exists file_ver.f ]} {
+    puts "---->using case dependent verilog file list"
+    set VLOG_SOURCE_LIST file_ver.f;
+}
+
+if {[file exists file_vhd.f ]} {
+    puts "---->using case dependent vhdl file list"
+    set VHDL_SOURCE_LIST file_vhd.f;
+}
+
+if {![string equal vhd $TOP_FILE_LANG]} {
+    set GLBL glbl
+}
+
+if {$SIM_TYPE == "timing"} {
+
+        set SDF_TYPE "-sdfmax";
+        set SDFCOM_TYPE "-maxdelays";
+
+    puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
+        if {[string equal $CORNER_TYPE "01_min" ]} {
+                set SDF_TYPE "-sdfmin";
+                set SDFCOM_TYPE "-mindelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "02_type" ]} {
+                set SDF_TYPE "-sdftyp";
+                set SDFCOM_TYPE "-typdelays";
+                puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "03_max" ]} {
+                set SDF_TYPE "-sdfmax";
+                set SDFCOM_TYPE "-maxdelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
+        }
+        
+        if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
+                puts "++++++++++ develop kit is libero ++++++++++";
+        } else {
+                puts "++++++++++ develop kit is not libero ++++++++++";
+                set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
+        }
+        
+        sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
+
+        #in timing simulation ,here only glbl may be compiled seperately
+    if {[file exists  ${VLOG_SOURCE_LIST}]} {
+        vlog  -incr -quiet  -sv  +cover=${COVERAGE_OPTION}  +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
+    }
+
+    vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
+
+    vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
+
+    eval vopt  ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
+        +initmem+0 +initreg+0 +initwire+0;
+
+
+    eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout  \
+    +no_notifier +no_tchk_msg\
+    work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
+        ${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
+
+    do ../suppresswarning.tcl
+
+
+    catch {run ${SIM_TIME} } res
+} else {
+
+
+#compile source files
+    if {[file exists ${VLOG_SOURCE_LIST}]} {
+        puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
+#       vlog -incr -quiet   +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+        vlog  -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+    }
+
+
+    if {[file exists ${VHDL_SOURCE_LIST}]} {
+        puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
+        vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
+    }
+
+#        eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
+#        +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
+#            +initmem+0 +initreg+0 +initwire+0 \
+#            -suppress 2912 \
+#            -suppress 1127
+
+    #to mask 211 error
+    catch {
+                if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
+                                eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
+                                        -t 1ps -wlfopt -wlfcompress -nostdout  \
+                                        +initmem+0 +initreg+0 +initwire+0 \
+                                        +no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
+                                        -classdebug \
+                                        glbl work.${CASE_NAME} \
+                                        -wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
+                } else {
+                        restart -f
+                }
+        } res;
+
+    do ../suppresswarning.tcl
+
+    catch {do wave.tcl} res
+
+    set TEMP_REF_FILES info.txt;
+    write report -l $TEMP_REF_FILES
+
+    catch {run ${SIM_TIME} } res
+
+    do ../saveucdb.tcl
+#}
+
+set current_path [pwd]
+puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
--- a/ssp_tx/sim/func001/runone.tcl
+++ b/ssp_tx/sim/func001/runone.tcl
@@ -0,0 +1,20 @@
+quit -sim
+cd ..
+
+#clear the simulator transcript window and make the wave,data & coverage director
+.main clear
+
+set wrap_args [list];
+#put the do command $1-$9 to list,because we can't use the argv,we should construct the "argv" mannully.
+for {set i 1} {$i <= $argc} {incr i 1} {
+    lappend wrap_args [set $i];
+}
+
+#echo $args
+
+eval do runone.tcl $wrap_args
+
+
+
+
+
--- a/ssp_tx/sim/func001/save.tcl
+++ b/ssp_tx/sim/func001/save.tcl
@@ -0,0 +1,7 @@
+if {$argc>=1} {
+    catch {write format wave -window Wave $1.tcl} res
+} else {
+    catch {write format wave -window Wave case.tcl} res
+}
+
+
--- a/ssp_tx/sim/func001/savewave.tcl
+++ b/ssp_tx/sim/func001/savewave.tcl
@@ -0,0 +1,114 @@
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {true} {
+    # raw script code in pre_format
+    set pre_format {
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+}
+}; list
+# from stackoverflow.com "how to keep commands quiet in TCL?"
+# if you want to inhibit such printouts in an interactive session(comes in handy from time to time), a simple hack to achieve that is to chain the command
+# you want to "silence" with a "silent" command(producing a value whose string representation is an empty string).
+# for instance: set a [open "giri.txt" r]; list
+
+if {true} {
+    # raw script code in post_format
+    set post_format {
+if { [info exists unset_CASE_NAME] && [string equal -nocase true $unset_CASE_NAME] } {
+    set unset_CASE_NAME false
+    unset CASE_NAME
+}
+}
+}; list
+
+# support save format when only open .wlf instead of run a case
+# When open .wlf file, there is no CASE_NAME variable in context. We get the case name by searching in the struct window instead.
+if {![info exists CASE_NAME]} {
+    puts "++++++++++ search case name ++++++++++"
+    set wave_sim_type func
+    for {set wave_i 0} {$wave_i < 1000} {incr wave_i 1} {
+        set wave_case_num [format "%03d" $wave_i];
+        set wave_case_name ${wave_sim_type}${wave_case_num}
+        if {[search structure $wave_case_name] >= 0} {
+            break
+        }
+    }
+    set unset_CASE_NAME true
+    set CASE_NAME $wave_case_name
+}
+
+# brace all to eliminate unnecessary output(example. "set fd_pre_savewave [open pre_savewave.tcl r]" will display returned value of set cmd)
+if {true} {
+    # save current wave format to a tmp file
+    catch {write format wave -window Wave intermediate_wave_format_file.tmp} res
+
+    if {$argc>=1} { # example: do savewave.tcl wave_name
+        set wave_name $1
+        if {[regexp {^([-\w\+]+\.)+[-\w\+]*$} $wave_name] >= 1} {
+            # replace the last postfix(.tcl or .do or .) with null, i.e. delete the last postfix(including .)
+            while {[regexp -nocase {(\.(tcl|do)*$)} $wave_name] >= 1} {
+                regsub {(\.[-\w\+]*$)} $wave_name {} wave_name
+            }
+        } elseif {[regexp {^[-\w\+]+$} $wave_name] >= 1} {
+            # nop
+        } else {
+            echo "Invalid file name $wave_name!"
+            return
+        }
+        set fd_wave [open $wave_name.tcl w]
+        echo "Wave format saved to $wave_name.tcl"
+    } else { # example: do savewave.tcl
+        set fd_wave [open wave1.tcl w]
+        echo "Wave format saved to wave1.tcl"
+    }
+
+    set fd_intermediate_wave_format_file [open intermediate_wave_format_file.tmp r]
+
+    # put lines in pre_format to final file(the file specified in argument $1)
+    set lines [split $pre_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in tmp file to final file(the file specified in argument $1)
+    while {[chan gets $fd_intermediate_wave_format_file wave_format_line] >= 0} {
+        if {[regexp -all {\[|\]} $wave_format_line] >= 1} {
+            # if [ and ] exist in line(like [10:0] or [2]), then escape them, i.e. \[ and \]
+            regsub -all {\[|\]} $wave_format_line {\\&} wave_format_line
+            # and then add eval in the biginning
+            regsub (^) $wave_format_line {eval } wave_format_line
+        }
+        # make virtual signal ok
+        if {[regexp -all {virtual signal} $wave_format_line] >= 1} {
+            regsub -all {\{} $wave_format_line {[subst &} wave_format_line
+            regsub -all {\}} $wave_format_line {&]} wave_format_line
+        }
+        regsub -all $CASE_NAME $wave_format_line {$CASE_NAME} wave_format_line
+        chan puts $fd_wave $wave_format_line
+    }
+
+    # put lines in post_format to final file(the file specified in argument $1)
+    set lines [split $post_format "\n"]
+    set total_lines [llength $lines]
+    for {set line_idx 0} {$line_idx < $total_lines} {incr line_idx 1} {
+        set wave_format_line [lindex $lines $line_idx]
+        chan puts $fd_wave $wave_format_line
+    }
+
+    close $fd_wave
+    close $fd_intermediate_wave_format_file
+}
--- a/ssp_tx/sim/func001/tb.sv
+++ b/ssp_tx/sim/func001/tb.sv
@@ -0,0 +1,73 @@
+`timescale 1ns/1ps
+
+module
+    `CASE_NAME();
+    `include "../instantiate_top.sv"
+	
+	final mti_fli::mti_Cmd("do ../saveucdb.tcl");
+
+    initial begin
+      $fsdbDumpfile("fsdb_wave.fsdb");
+      $fsdbDumpvars;
+    end
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>simulation time control>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/
+/*to end the simulation commandary*/
+/*if you want to end the simulation case by case,just comment the line
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<simulation time control<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/
+//TODO:
+
+
+    logic [7:0]  ssp_rx_tdata;
+    logic        ssp_rx_tvalid;
+    logic        ssp_rx_tready = 0;
+    logic [31:0] error_status;
+
+    // instance vip
+    vip_clock # (.FREQUENCY_MHZ(100)) u0_clock(.duty_percent(50), .jitter_percent(0), .clk(clk));
+    
+    vip_clock # (.FREQUENCY_MHZ(110)) u1_clock(.duty_percent(50), .jitter_percent(0), .clk(ssp_rx_clk));
+
+    ssp_rx # (
+        .FREQ_HZ(110e6),
+        .SSP_HZ(10e6)
+    ) u_ssp_rx (
+        .clk        (ssp_rx_clk),
+        .aresetn    (aresetn),
+
+        .tdata      (ssp_rx_tdata),
+        .tvalid     (ssp_rx_tvalid),
+        .tready     (ssp_rx_tready),
+
+        .ssp_clk    (ssp_clk),
+        .ssp_csn    (ssp_csn),
+        .ssp_data   (ssp_data),
+
+        .error_status (error_status)
+    );
+
+    initial begin
+        aresetn = 1'b0;
+        #200ns;
+        aresetn = 1'b1;
+    end
+
+    initial begin
+        tdata  = 8'h00;
+        tvalid = 1'b0;
+        wait (!aresetn);
+        #100ns;
+
+        repeat (20) begin
+            // send a byte
+            tvalid = 1'b1;
+            @(posedge tready) #1ns;
+            tvalid = 1'b0;
+            tdata++;
+        end
+
+        //$finish;
+    end
+
+		
+endmodule
--- a/ssp_tx/sim/func001/vip_clock.sv
+++ b/ssp_tx/sim/func001/vip_clock.sv
@@ -0,0 +1,29 @@
+module vip_clock
+    #(
+    parameter FREQUENCY_MHZ = 1,
+    parameter PHASE_DEGREE = 0
+    )
+    (
+    input int duty_percent = 50,//dynamical parameter
+    input int jitter_percent = 0,//dynamical parameter
+    output clk
+    );
+
+
+
+logic ideal_clk;
+
+initial begin
+    ideal_clk = 0;
+    #(1.0e3/FREQUENCY_MHZ/360.0*PHASE_DEGREE * 1ns);
+    forever begin
+        ideal_clk = 0;
+        #(1.0e3/FREQUENCY_MHZ*(1-duty_percent/100.0)* 1ns);
+
+        ideal_clk = 1;
+        #(1.0e3/FREQUENCY_MHZ*duty_percent/100.0 * 1ns);
+    end
+end
+
+assign # (1.0e3/FREQUENCY_MHZ*jitter_percent/100.0*1ns) clk =  ideal_clk;
+endmodule
--- a/ssp_tx/sim/func001/wave.tcl
+++ b/ssp_tx/sim/func001/wave.tcl
@@ -0,0 +1,75 @@
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+#preset envieroment variables
+if {[info exists SIM_TYPE] && $SIM_TYPE == "timing"} {
+    
+} else {
+
+    puts "---->checing the simulator status to decide whether to restore the wave session.................."
+    puts "---->the runstatus is :[runStatus]"
+    #if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "error" ]} {
+        puts "---->trying  restore to saved wave window.................."
+
+        catch {
+            set size [file size lastwave.tcl];
+            #check if size is too much
+            if($size > (10*1024){
+                puts "lastwave.tcl size is $size,try to recover"
+                do lastwave.tcl
+            }
+        } res;
+    #} 
+
+     
+    # catch {log -mvcreccomplete -r -depth 6  /* } res 
+    
+    catch {log -mvcreccomplete -r -depth 6  /$CASE_NAME/*} res 
+    catch {log -mvcreccomplete -r -depth 6  /$CASE_NAME/$TOP_INSTANCE/*} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/CENTRAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/TRAIN_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/SEQUENCER_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRX_inst/GENIMGVAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGRXDATA_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_AREF_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_INIT_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_READ_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instHigh/SDRAM_WRITE_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_TOP_instLow} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/SDRAM_FRMRDCTRL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGTX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/IMGSPI_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/COMMANDHANDLER_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/ERUPRAMCAL_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/ERUPSUM_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/FRMHEADWR_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/GUIDEPIEZORX_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/STATE_RETURN_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TEMP461_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIME_TICK_inst} res 
+    # catch {log -mvcreccomplete -r -depth 4  /$CASE_NAME/$TOP_INSTANCE/TIMEPRO_inst} res 
+	
+	
+	
+#   log -class pkg_uart::uart
+#   catch {class/pkg_uart::uart::uart__2} res;
+}
--- a/ssp_tx/sim/functions.tcl
+++ b/ssp_tx/sim/functions.tcl
@@ -0,0 +1,39 @@
+#usage: "do xxx.tcl timing" for timing simulation and "do xxx.tcl" for functional simulation
+
+#get the current script file name by [info frame],walk through all frame return lines
+#here we use the "do ..." command to start this script,so we can't use the [info script]
+#command to start this script
+#with the "do ..." command,we can start this script with command line options,and we 
+#can refercen these options by $1,$2,etc.
+proc get_file_name { } {
+
+    set file_name 0
+    catch {
+       set max_info [info frame]
+       puts "maxinfo=$max_info"
+        puts "...................................."
+       for {set a $max_info} {$a>0} {incr a -1} {
+            puts $a
+            set framestring [info frame $a];
+            puts $framestring;
+            set cmdstring [dict get $framestring cmd];                  #extract command with "cmd" key
+            if {[string match *case*.tcl* $cmdstring]} {                     #search "do xxx.tcl timing" patten
+                puts $cmdstring
+                set ary [split $cmdstring " "]
+                puts $ary
+                set file_name [lindex $ary 1]
+                puts $file_name
+                break
+            }
+        }
+    }
+    return $file_name
+}
+
+
+proc get_case_num {case_name} {
+    regsub {[a-z]*} $case_name {} case_num
+#   puts $case_num
+    return $case_num
+}
+
--- a/ssp_tx/sim/glbl.v
+++ b/ssp_tx/sim/glbl.v
@@ -0,0 +1,66 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
--- a/ssp_tx/sim/globalset.tcl
+++ b/ssp_tx/sim/globalset.tcl
@@ -0,0 +1,56 @@
+    
+
+#TODO:set the top module name with extention
+set TOP_FILE ssp_tx.sv
+
+#TODO:set the top entity architecuture,vhdl file only;If the top module file is verilog,just ignore this var
+set TOP_VHD_ARCH Behavioral
+
+#TODO:set the coverage collect option
+set COVERAGE_OPTION sbfce
+
+#TODO:set the root path of simlation library,relative to the run.tcl
+set SIM_LIB_ROOT  ../../../../../../03_simlib
+#set SIM_LIB_ROOT d:/02_work/simlib
+
+#TODO:sset the simulator excutable path
+set SIM_TOOL_PATH c:/questasim64_10.7
+
+#TODO: device family, microsemi/actel only
+set ACTEL_FAMILY proasic3l
+
+#TODO:set simulator name
+set SIMULATOR questasim
+#TODO:set simulator verion
+set SIMULATOR_VER 10.7
+#TODO:set simulator platform
+set SIMULATOR_PLATFORM nt64
+#TODO:set fpga par tools
+set FPGA_KIT_VER libero11.8
+#TODO:set vhdl library full path
+#set VHDL_LIB $SIM_LIB_ROOT/vhdl/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
+#TODO:set verilog library full pth
+#set VLOG_LIB $SIM_LIB_ROOT/verilog/$SIMULATOR/$SIMULATOR_VER/$SIMULATOR_PLATFORM/$FPGA_KIT_VER
+
+
+file mkdir coverage
+file mkdir wave
+file mkdir data
+file mkdir work
+
+#DO NOT MODIFYset the coverage data dirctory,relative to the run.tcl
+set COVERAGE_OUTPUT_DIR ../coverage
+#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
+set WAVE_OUTPUT_DIR ../wave
+#DO NOT MODIFYset the wave data dirctory,relative to the run.tcl
+set WORK_LIB_DIR ../work
+#DO NOT MODIFYget the top most module name
+set TOP_ENTITY [file rootname ${TOP_FILE}]
+#DO NOT MODIFYget the top most module language,vhdl or verilog
+set TOP_FILE_LANG [file extension  ${TOP_FILE}]
+#DO NOT MODIFYse the top most instance name,with "u0_" prefix
+set TOP_INSTANCE u0_${TOP_ENTITY}
+
+
+
+
--- a/ssp_tx/sim/instantiate_top.sv
+++ b/ssp_tx/sim/instantiate_top.sv
@@ -0,0 +1,33 @@
+/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/ 
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*add all port here*/                                                            
+/*use "logic" to replace "logic" and "logic" ports*/                            
+/*use "wire" to replace "inout" ports*/                                          
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+//TODO:                                                                          	
+
+
+ logic        clk;
+ logic        aresetn;
+
+ logic [7:0]  tdata;
+ logic        tvalid;
+ logic        tready;
+
+ logic        ssp_clk;
+ logic        ssp_csn;
+ logic        ssp_data;
+
+ logic        ssp_tx_busy;
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/   
+/*initialize all "logic" ports here                                                         
+/*all inputs default as 0,modify if necessary                                               
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/   
+//TODO:
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+                                                                                            
+/*do not modify
+*/
+`TOP_ENTITY `TOP_INSTANCE(.*);
--- a/ssp_tx/sim/mergeucdb.tcl
+++ b/ssp_tx/sim/mergeucdb.tcl
@@ -0,0 +1,16 @@
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+source globalset.tcl
+
+if {[info exists TOP_FILE_LANG] && ![string compare ${TOP_FILE_LANG} ".vhd"]} {
+vcover merge -stats=none -strip 0 -du [string tolower ${TOP_ENTITY}]([string tolower ${TOP_VHD_ARCH}]) -recursive  -totals merge.ucdb  ./coverage/*.ucdb
+} else {
+    vcover merge -stats=none -strip 0 -du ${TOP_ENTITY} -recursive  -totals merge.ucdb  ./coverage/*.ucdb
+}
--- a/ssp_tx/sim/modelsim.ini
+++ b/ssp_tx/sim/modelsim.ini
--- a/ssp_tx/sim/parse_args.tcl
+++ b/ssp_tx/sim/parse_args.tcl
@@ -0,0 +1,147 @@
+
+set SIM_TYPE func  ;
+set CASE_NUM 1   ;
+set SIM_TIME 100sec  ;#as all
+set CORNER_TYPE max ;
+set COPY_RUN_TEMPLATE no;
+
+#declear a empty list 
+
+set args [list];
+#put the do command $1-$9 to list,because we can't use the argv,we should construct the "argv" mannully.
+for {set i 1} {$i <= $argc} {incr i 1} {
+    lappend args [set $i];
+}
+puts "---->parsing the command line....argc=$argc,args=$args*************************"
+
+#get the max index of the list,the "expr" command should be use to calculate out the express
+set max_index  [expr  $argc-1];
+
+#search copy templation option
+for {set i 0} {$i < $argc} {incr i 1} {
+
+    set para [lindex  $args $i]
+    if {[string equal $para "-c"]} {
+        set COPY_RUN_TEMPLATE yes
+        puts "whether to copy run.tcl template=$COPY_RUN_TEMPLATE"
+        break;
+    }
+}
+
+#search generate instantiate_top.sv opton
+for {set i 0} {$i < $argc} {incr i 1} {
+
+    set para [lindex  $args $i]
+    if {[string equal $para "-g"]} {
+        set GEN_INSTANTIATE_TOP yes
+        puts "force generate instantiate_top.sv and override exist file"
+        break;
+    }
+}
+
+#search case number
+for {set i 0} {$i < $argc} {incr i 1} {
+     set para [lindex  $args $i];
+     if {[string equal $para "-n"] } {
+
+        if {$i < $max_index} {
+            set num [lindex $args [expr [expr $i+1]]];
+            if { [string is digit $num] } {
+                set CASE_NUM [format "%03d" $num];
+                puts "case number=$CASE_NUM"
+            }
+            break;
+        }
+    }
+}
+
+#search simulation time
+for {set i 0} {$i < $argc} {incr i 1} {
+
+    set para [lindex  $args $i]
+    if {[string equal $para "-t"]} {
+        if {$i < $max_index} {
+            set time [lindex $args [expr $i+1]]
+            if {[regexp {^[0-9]+((n|u|m)s|sec)$} $time]} {
+                set SIM_TIME $time
+                puts "simulation time=$SIM_TIME"
+            } else {
+                puts "unknow simulation time,set to 1us"
+                set SIM_TIME 1us
+                puts "simulation time=$SIM_TIME"
+
+            }
+            break;
+        }
+    }
+}
+
+#search simulation type
+for {set i 0} {$i < $argc} {incr i 1} {
+
+    set para [lindex  $args $i]
+    if {[string equal $para "-timing"]} {
+        set SIM_TYPE "timing"
+        puts "simulation type=$SIM_TYPE"
+        break;
+    } elseif {[string equal $para "-func"]} {
+        set SIM_TYPE "func"
+        puts "simulation type=$SIM_TYPE"
+        break;
+    }
+}
+
+
+#search corner type 
+for {set i 0} {$i < $argc} {incr i 1} { 
+
+    set para [lindex  $args $i] 
+    if {[string equal $para "-corner"]} { 
+        if {$i < $max_index } { 
+            set corner [lindex $args [expr $i+1]] 
+
+            #处理run.tcl中再次调用本脚本导致的bug ,删除前导的数字
+            regsub -nocase {[0-9]+_} $corner "" corner 
+
+            switch -glob  $corner { 
+                "max" { 
+                    set CORNER_TYPE 03_max 
+                } 
+                "min" { 
+                    set CORNER_TYPE 01_min 
+                } 
+                "type" { 
+                    set CORNER_TYPE 02_type 
+                } 
+                default { 
+                    puts "unknow corner type,set to 03_max" 
+                    set CORNER_TYPE 03_max 
+                } 
+
+            } 
+            puts "corner type=$CORNER_TYPE" 
+            break; 
+        } 
+    } 
+} 
+
+
+
+#search simulation type
+for {set i 0} {$i < $argc} {incr i 1} {
+
+    set para [lindex  $args $i]
+    if {[string equal $para "-h"]} {
+        puts "------------------------help------------------------"
+        puts "-n x:specify case number to be excuted,x stand for case number,default to 0"
+        puts "-t x:specify simulation time to be excuted,x stand for time,unit may be ns,us,ms,sec,default to 1us"
+        puts "-timing:specify to excute in timing simulation mode"
+        puts "-corner x:specify the timing simulation corner,may be max,min,type,default to max"
+        puts "-c:force to override run.tcl scripts in case directory,be carefull"
+        puts "-h:to display this help information,it has the highest priority,thus block other options"
+        puts "----------------------------------------------------"
+        return 0;
+    }
+}
+
+puts "---->parsing the command line complete ***************************"
--- a/ssp_tx/sim/run_template.tcl
+++ b/ssp_tx/sim/run_template.tcl
@@ -0,0 +1,227 @@
+#quit -sim
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#unbound the the "work" lib dir from vsim,to remove it
+
+#when error do not save wave list
+if {![string compare [runStatus] "ready" ] || ![string compare [runStatus] "break" ]} {
+    source savewave.tcl
+}
+#catch {q -sim} res
+#dataset close -all
+
+echo on
+.main clear
+
+puts "+++++++++++++++++++++++++++++++++++++++$CASE_NAME start+++++++++++++++++++++++++++++++++++++++"
+
+vmap std $SIM_TOOL_PATH/std  ;
+vmap ieee $SIM_TOOL_PATH/ieee   ;
+
+set FUNC_SOURCE_DIR   ../../../01_source/01_func
+set TIMING_SOURCE_DIR ../../../01_source/02_timing
+
+set source_vhdl false
+set source_verilog false
+
+set LIB_OPTION ""
+set LOG_OPTION ""
+
+#if {[string match -nocase {libero*} $FPGA_KIT_VER]} {
+#    #-----------actel----------
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    if {[string equal -nocase vhd $TOP_FILE_LANG]} {
+#        vmap ${ACTEL_FAMILY} $VHDL_LIB/${ACTEL_FAMILY};
+#    } else {
+#        vmap ${ACTEL_FAMILY} $VLOG_LIB/${ACTEL_FAMILY};
+#    }
+#    set LIB_OPTION "-L ${ACTEL_FAMILY}"
+#
+#} elseif {[string match -nocase {ise*} $FPGA_KIT_VER]} {
+#    #puts "IDE IS $FPGA_KIT_VER!"
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.vhd] {
+#        set source_vhdl true
+#		set LOG_OPTION "-vhdlvariablelogging"
+#    }
+#    foreach file [glob -nocomplain -directory $FUNC_SOURCE_DIR *.v] {
+#        set source_verilog true
+#    }
+#    if { [string equal -nocase true $source_vhdl] } {
+#        #-----------xilinx vhdl----------
+#        #puts "vhdl file exist!"
+#        vmap simprim       $VHDL_LIB/simprim
+#        vmap unisim        $VHDL_LIB/unisim
+#        vmap xilinxcorelib $VHDL_LIB/xilinxcorelib
+#        vmap unimacro      $VHDL_LIB/unimacro
+#        set LIB_OPTION "-L simprim -L unisim -L xilinxcorelib -L unimacro"
+#    }
+#
+#    if { [string equal -nocase true $source_verilog] } {
+#        #-----------xilinx verilog----------
+#        #puts "verilog file exist!"
+#        vmap unisims_ver       $VLOG_LIB/unisims_ver
+#        vmap simprims_ver      $VLOG_LIB/simprims_ver
+#        vmap xilinxcorelib_ver $VLOG_LIB/xilinxcorelib_ver
+#        vmap unimacro_ver      $VLOG_LIB/unimacro_ver
+#        vmap secureip          $VLOG_LIB/secureip
+#        set LIB_OPTION "-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L unimacro_ver -L secureip"
+#    }
+#}
+
+set defs [dict create;] ;
+dict append defs CASE_NAME $CASE_NAME;
+dict append defs TOP_ENTITY $TOP_ENTITY;
+dict append defs TOP_INSTANCE $TOP_INSTANCE;
+dict append defs timing;
+dict append defs SIM_TIME $SIM_TIME ;
+
+set def_string "";
+dict for {def_name def_value} $defs {
+    set def_string [format "%s+define+%s=%s" $def_string $def_name $def_value;];
+}
+puts "the define string is:$def_string"
+
+
+#file delete -force work            ;
+
+vlib $WORK_LIB_DIR/${CASE_DIR};
+vmap work $WORK_LIB_DIR/${CASE_DIR};
+catch { file delete -force $WORK_LIB_DIR/${CASE_DIR}/_lock        } res;
+catch {file delete -force $WORK_LIB_DIR/${CASE_DIR}/     } res;
+
+#if {![info exists SIM_TYPE]} {set SIM_TYPE func}
+#if {![info exists CORNER_TYPE]} {set CORNER_TYPE 03_max}
+
+#if {[info exists 1]} {
+#    set SIM_TIME $1
+#} elseif {![info exists SIM_TIME]} {set SIM_TIME -all}
+
+
+
+#by default,all cases use the same source file list
+set VLOG_SOURCE_LIST ../file_ver.f;
+set VHDL_SOURCE_LIST ../file_vhd.f;
+
+#we specify individual file list for single case
+if {[file exists file_ver.f ]} {
+    puts "---->using case dependent verilog file list"
+    set VLOG_SOURCE_LIST file_ver.f;
+}
+
+if {[file exists file_vhd.f ]} {
+    puts "---->using case dependent vhdl file list"
+    set VHDL_SOURCE_LIST file_vhd.f;
+}
+
+if {![string equal vhd $TOP_FILE_LANG]} {
+    set GLBL glbl
+}
+
+if {$SIM_TYPE == "timing"} {
+
+        set SDF_TYPE "-sdfmax";
+        set SDFCOM_TYPE "-maxdelays";
+
+    puts "*************************timing simulation for CORNER_TYPE= $CORNER_TYPE*************************"
+        if {[string equal $CORNER_TYPE "01_min" ]} {
+                set SDF_TYPE "-sdfmin";
+                set SDFCOM_TYPE "-mindelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmin ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "02_type" ]} {
+                set SDF_TYPE "-sdftyp";
+                set SDFCOM_TYPE "-typdelays";
+                puts "++++++++++ set SDF_TYPE = -sdftyp ++++++++++";
+        } elseif {[string equal $CORNER_TYPE "03_max" ]} {
+                set SDF_TYPE "-sdfmax";
+                set SDFCOM_TYPE "-maxdelays";
+                puts "++++++++++ set SDF_TYPE = -sdfmax ++++++++++";
+        }
+        
+        if {[string match -nocase "libero*" $FPGA_KIT_VER]} {
+                puts "++++++++++ develop kit is libero ++++++++++";
+        } else {
+                puts "++++++++++ develop kit is not libero ++++++++++";
+                set TIMING_SOURCE_DIR ${TIMING_SOURCE_DIR}/${CORNER_TYPE}
+        }
+        
+        sdfcom $SDFCOM_TYPE $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdf $TIMING_SOURCE_DIR/${TOP_ENTITY}.sdfcom
+
+        #in timing simulation ,here only glbl may be compiled seperately
+    if {[file exists  ${VLOG_SOURCE_LIST}]} {
+        vlog  -incr -quiet  -sv  +cover=${COVERAGE_OPTION}  +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string
+    }
+
+    vlog -quiet +cover=${COVERAGE_OPTION} -work work ${TIMING_SOURCE_DIR}/*.v
+
+    vlog -quiet -sv +cover=${COVERAGE_OPTION} -work work tb.sv $def_string
+
+    eval vopt  ${GLBL} ${CASE_NAME} +acc=npr ${LIB_OPTION} -o ${CASE_NAME}_opt \
+        +initmem+0 +initreg+0 +initwire+0;
+
+
+    eval vsim -batch -quiet ${LIB_OPTION} -t 100ps -wlfopt -wlfcompress -nostdout  \
+    +no_notifier +no_tchk_msg\
+    work.${CASE_NAME}_opt -wlf ${WAVE_OUTPUT_DIR}/${CASE_NAME}_timing.wlf +notimingchecks \
+        ${SDF_TYPE} ${CASE_NAME}/${TOP_INSTANCE}=${TIMING_SOURCE_DIR}/${TOP_ENTITY}.sdfcom;
+
+    do ../suppresswarning.tcl
+
+
+    catch {run ${SIM_TIME} } res
+} else {
+
+
+#compile source files
+    if {[file exists ${VLOG_SOURCE_LIST}]} {
+        puts "---->compile verilog source files ,testbench and models using $VLOG_SOURCE_LIST........"
+#       vlog -incr -quiet   +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+        vlog  -sv -vmake -quiet +cover=${COVERAGE_OPTION} +incdir+../ -work work -f ${VLOG_SOURCE_LIST} $def_string -suppress 12003
+    }
+
+
+    if {[file exists ${VHDL_SOURCE_LIST}]} {
+        puts "---->compile vhdl files using $VHDL_SOURCE_LIST........"
+        vcom -vmake -nocoverudp -2008 -explicit -quiet +cover=${COVERAGE_OPTION} -work work -f ${VHDL_SOURCE_LIST}
+    }
+
+#        eval vopt ${GLBL} ${CASE_NAME} +acc -o ${CASE_NAME}_opt ${LIB_OPTION} \
+#        +cover=bcsf+/${CASE_NAME}/${TOP_INSTANCE} -nocoverudp -nocovercells \
+#            +initmem+0 +initreg+0 +initwire+0 \
+#            -suppress 2912 \
+#            -suppress 1127
+
+    #to mask 211 error
+    catch {
+                if { [string compare [runStatus] "ready" ] && [string compare [runStatus] "break" ]} {
+                                eval vsim ${LOG_OPTION} -batch -quiet -coverage -voptargs="+acc=npr" ${LIB_OPTION} \
+                                        -t 1ps -wlfopt -wlfcompress -nostdout  \
+                                        +initmem+0 +initreg+0 +initwire+0 \
+                                        +no_notifier +no_tchk_msg -suppress 3009 -suppress 12110 \
+                                        -classdebug \
+                                        glbl work.${CASE_NAME} \
+                                        -wlf ${WAVE_OUTPUT_DIR}/${CASE_DIR}_timeing.wlf
+                } else {
+                        restart -f
+                }
+        } res;
+
+    do ../suppresswarning.tcl
+
+    catch {do wave.tcl} res
+
+    set TEMP_REF_FILES info.txt;
+    write report -l $TEMP_REF_FILES
+
+    catch {run ${SIM_TIME} } res
+
+    do ../saveucdb.tcl
+#}
+
+set current_path [pwd]
+puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
--- a/ssp_tx/sim/runall.tcl
+++ b/ssp_tx/sim/runall.tcl
@@ -0,0 +1,15 @@
+#usage do runall.tcl 1ms
+
+set ROOT_PATH [pwd]
+
+for {set NUMBER 3} { $NUMBER < 14} {incr NUMBER} {
+    set CASE_NUMBER [format "%03d" $NUMBER]
+    puts ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>$CASE_NUMBER start>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>"
+    catch {do runone.tcl -n $CASE_NUMBER -t $1} result
+    quit -sim
+    cd ${ROOT_PATH}
+    puts "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<$CASE_NUMBER end<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
+} 
+
+
+
--- a/ssp_tx/sim/runone.tcl
+++ b/ssp_tx/sim/runone.tcl
@@ -0,0 +1,80 @@
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+
+
+#clear the simulator transcript window and make the wave,data & coverage director
+do clear.tcl
+#preset envieroment variables
+do globalset.tcl
+set ROOT_PATH [pwd];
+
+
+#import common routines
+source functions.tcl
+source parse_args.tcl;
+
+
+set CASE_DIR ${SIM_TYPE}${CASE_NUM}
+
+#we discard the case_num,thus all cases use the same case name.
+#thus the signal_name in the lastwave.tcl will be case independent
+#it's convinient to share and inherit lastwave in different case
+set CASE_NAME ${SIM_TYPE}${CASE_NUM}
+
+
+#puts "SIM_TYPE   =  $SIM_TYPE  "
+#puts "CASE_NUM   =  $CASE_NUM  "
+#puts "SIM_TIME   =  $SIM_TIME  "
+#puts "CORNER_TYPE =  $CORNER_TYPE"
+#puts "CASE_NAME  =  $CASE_NAME "
+
+#copy modelsim.ini to case dir,and enter the case dependent directory
+file copy -force modelsim.ini ./${CASE_DIR}
+
+
+#by default,all cases use the same run.tcl
+#we can make trivial change to each case
+
+
+file copy -force run_template.tcl ./${CASE_DIR}/run.tcl
+
+#we can use -c command to override run.tcl
+puts "---->check if override the run.tcl commandary..............."
+if {[string equal $COPY_RUN_TEMPLATE "yes" ]} {
+file copy -force run_template.tcl ./${CASE_DIR}/run.tcl
+puts "<<<<<<<<<<force copy run_template.tcl to ${CASE_DIR} dirctory>>>>>>>>>"
+}
+
+#force generate instantiate_top.sv and override exist file
+if {[info exists GEN_INSTANTIATE_TOP]  && [string equal $GEN_INSTANTIATE_TOP "yes" ]} {
+    exec python ../../../../../python/gen_instantiate_top.py ../../01_source/01_func/${TOP_FILE}
+}
+
+if {![file exists ./instantiate_top.sv]} {
+    exec python ../../../../../python/gen_instantiate_top.py ../../01_source/01_func/${TOP_FILE}
+}
+
+cd ${CASE_DIR}
+if { [ catch {do run.tcl -t $SIM_TIME -type $SIM_TYPE -corner $CORNER_TYPE} result ] } {
+    
+    quit -sim
+    cd ${ROOT_PATH}
+
+    }
+
+set current_path [pwd]
+puts "+++++++++++++++++++++++++++current path=$current_path++++++++++++++++++++++++++++++++"
+
--- a/ssp_tx/sim/saveucdb.tcl
+++ b/ssp_tx/sim/saveucdb.tcl
@@ -0,0 +1,14 @@
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+#ATTTION : DO NOT MODIFY THE WHOLE FILE
+
+
+coverage save ${COVERAGE_OUTPUT_DIR}/${CASE_NAME}.ucdb
--- a/ssp_tx/sim/start_questasim_here.cmd
+++ b/ssp_tx/sim/start_questasim_here.cmd
@@ -0,0 +1,8 @@
+
+del  /f /q transcript
+start c:\questasim64_10.7\win64\questasim.exe -do sstc.preference
+rem start C:\questasim64_10.4c\win64\questasim.exe -do sstc.preference
+rem start D:\questasim64_10.7\win64\questasim.exe
+rem vsim -batch -logfile this.log
+
+rem vsim -c
--- a/ssp_tx/sim/suppresswarning.tcl
+++ b/ssp_tx/sim/suppresswarning.tcl
@@ -0,0 +1,21 @@
+
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+#ATTTION : MODIFY THIS FILE AS YOU WANT
+
+
+#0=note,1=warning,2=error,3=failure,4=fatal
+#   set BreakOnAssertion 3        ;
+#   set IgnoreNote 1              ;
+#   set IgnoreWarning 1           ;
+#   #set IgnoreError 1            ;
+#   #set IgnoreFailure 1          ;
+#   set IgnoreSVAInfo 1           ;
+#   set IgnoreSVAWarning 1        ;
+#   #set IgnoreSVAError 1         ;
+#   #set IgnoreSVAFatal 1         ;
+#   set NumericStdNoWarnings  1   ;
+#   set StdArithNoWarnings    1   ;
--- a/ssp_tx/sim/transcript
+++ b/ssp_tx/sim/transcript
@@ -0,0 +1,99 @@
+# Reading C:/questasim64_10.7/tcl/vsim/pref.tcl
+# //  Questa Sim-64
+# //  Version 10.7 win64 Dec  7 2017
+# //
+# //  Copyright 1991-2017 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# sstc.preference
+# invalid command name "sstc.preference"
+do runone.tcl -n 1 -t 20us
+# on
+# ssp_tx.sv
+# Behavioral
+# sbfce
+# ../../../../../../03_simlib
+# c:/questasim64_10.7
+# proasic3l
+# questasim
+# 10.7
+# nt64
+# libero11.8
+# ../coverage
+# ../wave
+# ../work
+# ssp_tx
+# .sv
+# u0_ssp_tx
+# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim
+# ---->parsing the command line....argc=4,args=-n 1 -t 20us*************************
+# case number=001
+# simulation time=20us
+# ---->parsing the command line complete ***************************
+# func001
+# func001
+# ---->check if override the run.tcl commandary...............
+# reading modelsim.ini
+# on
+# +++++++++++++++++++++++++++++++++++++++func001 start+++++++++++++++++++++++++++++++++++++++
+# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
+# vmap std c:/questasim64_10.7/std 
+# Modifying modelsim.ini
+# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
+# vmap ieee c:/questasim64_10.7/ieee 
+# Modifying modelsim.ini
+# ../../../01_source/01_func
+# ../../../01_source/02_timing
+# false
+# false
+# CASE_NAME func001
+# CASE_NAME func001 TOP_ENTITY ssp_tx
+# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx
+# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx timing {}
+# CASE_NAME func001 TOP_ENTITY ssp_tx TOP_INSTANCE u0_ssp_tx timing {} SIM_TIME 20us
+# the define string is:+define+CASE_NAME=func001+define+TOP_ENTITY=ssp_tx+define+TOP_INSTANCE=u0_ssp_tx+define+timing=+define+SIM_TIME=20us
+# QuestaSim-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec  7 2017
+# vmap work ../work/func001 
+# Modifying modelsim.ini
+# 0
+# 0
+# ../file_ver.f
+# ../file_vhd.f
+# glbl
+# ---->compile verilog source files ,testbench and models using ../file_ver.f........
+# ** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
+# ** Warning: tb.sv(7): (vlib-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
+# vsim -quiet -coverage -voptargs=""+acc=npr"" -t 1ps -wlfopt -wlfcompress -nostdout "+initmem+0" "+initreg+0" "+initwire+0" "+no_notifier" "+no_tchk_msg" -suppress 3009 -suppress 12110 -classdebug glbl work.func001 -wlf ../wave/func001_timeing.wlf 
+# Start time: 14:35:39 on Oct 16,2025
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Note: (vopt-143) Recognized 1 FSM in module "ssp_tx(fast)".
+# ** Note: (vopt-143) Recognized 1 FSM in module "ssp_rx(fast)".
+# ** Warning: tb.sv(7): (vopt-2240) Treating stand-alone use of function 'mti_Cmd' as an implicit VOID cast.
+# ** Warning: func001.u_ssp_rx.genblk1: FREQ_HZ/SSP_HZ is not an even number, which means the SSP clock will be asymmetric!
+#    Time: 0 ps  Scope: func001.u_ssp_rx.genblk1 File: ../../../ssp_rx/src/ssp_rx.sv Line: 30
+# ** Warning: (vsim-PLI-3003) tb.sv(10): [TOFD] - System task or function '$fsdbDumpfile' is not defined.
+#    Time: 0 ps  Iteration: 0  Instance: /func001 File: tb.sv
+# ** Warning: (vsim-PLI-3003) tb.sv(11): [TOFD] - System task or function '$fsdbDumpvars' is not defined.
+#    Time: 0 ps  Iteration: 0  Instance: /func001 File: tb.sv
+# ---->checing the simulator status to decide whether to restore the wave session..................
+# ---->the runstatus is :ready
+# ---->trying  restore to saved wave window..................
+# 0
+# ** Error (suppressible): (vsim-12023) tb.sv(10): Cannot execute undefined system task/function '$fsdbDumpfile'
+# ** Error (suppressible): (vsim-12023) tb.sv(11): Cannot execute undefined system task/function '$fsdbDumpvars'
+# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001
+# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001++++++++++++++++++++++++++++++++
+# C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001
+# +++++++++++++++++++++++++++current path=C:/Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_tx/sim/func001++++++++++++++++++++++++++++++++
+add wave -position insertpoint sim:/func001/u0_ssp_tx/*
+add wave -position insertpoint sim:/func001/u_ssp_rx/*
+# End time: 14:38:31 on Oct 16,2025, Elapsed time: 0:02:52
+# Errors: 2, Warnings: 4
--- a/ssp_tx/sim/wave/func001_timeing.wlf
+++ b/ssp_tx/sim/wave/func001_timeing.wlf
--- a/ssp_tx/src/component.xml
+++ b/ssp_tx/src/component.xml
@@ -0,0 +1,537 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>ssp_tx</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>interface_axis</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TKEEP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tkeep</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TLAST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tlast</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>tready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">interface_axis</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>SystemVerilog</spirit:language>
+        <spirit:modelName>ssp_tx</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>888b0c15</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>SystemVerilog</spirit:language>
+        <spirit:modelName>ssp_tx</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>888b0c15</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>73301cb5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">7</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tkeep</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tstrb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tlast</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>tready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ssp_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ssp_csn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ssp_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ssp_tx_busy</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>config_00</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>config_01</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>status_00</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>status_01</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>status_02</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>FREQ_HZ</spirit:name>
+        <spirit:displayName>Freq Hz</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREQ_HZ">100000000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SSP_HZ</spirit:name>
+        <spirit:displayName>Ssp Hz</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SSP_HZ">10000000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_9d8b0d81</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>wall_timer.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ssp_tx.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_ce7decc3</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>wall_timer.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>ssp_tx.sv</spirit:name>
+        <spirit:fileType>systemVerilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/ssp_tx_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_73301cb5</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>ssp_tx_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>FREQ_HZ</spirit:name>
+      <spirit:displayName>Freq Hz</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ">100000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SSP_HZ</spirit:name>
+      <spirit:displayName>Ssp Hz</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SSP_HZ">10000000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ssp_tx_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>ssp_tx_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>package_project</xilinx:definitionSource>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2026-02-03T10:02:02Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="nopcore"/>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2023.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="d9ac155a"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7ef768ec"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="66c181c2"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f333f548"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="25c05a5c"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
--- a/ssp_tx/src/ssp_tx.sv
+++ b/ssp_tx/src/ssp_tx.sv
@@ -0,0 +1,266 @@
+//---------------------------------------------------------------------------------------
+//    filename: ssp_tx.sv
+// description: synchronous serial peripheral interface transmitter
+//      author: leguoqing@paisat.cn
+//---------------------------------------------------------------------------------------
+
+module ssp_tx #(
+    parameter integer FREQ_HZ = 100e6,
+    parameter integer SSP_HZ  = 10e6
+) (
+    input  logic        clk,
+    input  logic        aresetn,
+
+    input  logic [7:0]  tdata,
+    input  logic        tvalid,
+    input  logic        tkeep,
+    input  logic        tstrb,
+    input  logic        tlast,
+    output logic        tready,
+
+    output logic        ssp_clk,
+    output logic        ssp_csn,
+    output logic        ssp_data,
+
+    output logic        ssp_tx_busy,
+
+    input  logic [31:0] config_00,
+    input  logic [31:0] config_01,
+
+    output logic [31:0] status_00,
+    output logic [31:0] status_01,
+    output logic [31:0] status_02
+);
+
+    if ($ceil(FREQ_HZ/SSP_HZ) != $floor(FREQ_HZ/SSP_HZ)) begin
+        $fatal("%m: FREQ_HZ must be an integer multiple of SSP_HZ!");
+    end else if (FREQ_HZ/SSP_HZ < 6) begin
+        $fatal("%m: FREQ_HZ/SSP_HZ < 6!");
+    end else if ((FREQ_HZ/SSP_HZ)%2 != 0) begin
+        $warning("%m: FREQ_HZ/SSP_HZ is not an even number, which means the SSP clock will be asymmetric!");
+    end
+
+    localparam integer CLK_HI = $ceil(FREQ_HZ/(2*SSP_HZ));
+    localparam integer CLK_LO = $floor(FREQ_HZ/(2*SSP_HZ));
+
+    localparam integer SEP_BYTES = 1; // Number of byte times to wait between transmissions
+    localparam integer TIMER_US_WIDTH = 32;
+
+    // State encoding
+    typedef enum logic [1:0] {
+        IDLE,
+        TRANSMIT,
+        LAST,
+        SEP
+    } state_t;
+
+    state_t state, state_next;
+
+    logic [ 7:0] fsm_hardcode;
+    logic [31:0] counter_tx_data;
+    logic [31:0] counter_tx_last;
+
+    // Clock divider
+    logic [23:0] clk_div;
+
+    logic [7:0]              tx_shift_reg;
+    logic [2:0]              tx_bit_cnt;
+    logic [23:0]             last_divider;
+
+    logic timer_enable;
+    logic timeout;
+    logic [TIMER_US_WIDTH-1:0] timer_us;
+
+    logic [TIMER_US_WIDTH-1:0] min_sep_us;
+    logic [23:0]               cfg_divider;
+
+    assign min_sep_us  = config_00[0+:TIMER_US_WIDTH];
+    assign cfg_divider = config_01;
+
+    assign status_00 = {16'h0, fsm_hardcode, 8'h1};
+    assign status_01 = counter_tx_data;
+    assign status_02 = counter_tx_last;
+
+    always_ff @(posedge clk) begin
+        if (~aresetn) begin
+            fsm_hardcode <= 0;
+        end else begin
+            case (state)
+                IDLE:
+                    fsm_hardcode <= 8'h0;
+                TRANSMIT:
+                    fsm_hardcode <= 8'h1;
+                LAST:
+                    fsm_hardcode <= 8'h2;
+                SEP:
+                    fsm_hardcode <= 8'h3;
+                default:
+                    fsm_hardcode <= 8'hF;
+            endcase
+        end
+    end
+
+    // FSM: State register
+    always_ff @(posedge clk) begin
+        if (!aresetn) begin
+            state <= IDLE;
+        end else begin
+            state <= state_next;
+        end
+    end
+
+    // FSM: Next state logic
+    always_comb begin
+        state_next = state;
+        case (state)
+            IDLE: begin
+                if (tvalid & tkeep && clk_div == last_divider) begin
+                    if (tlast)
+                        state_next = LAST;
+                    else
+                        state_next = TRANSMIT;
+                end
+            end
+            TRANSMIT: begin
+                if (tx_bit_cnt == 3'h7 && clk_div == last_divider) begin
+                    if (tvalid)
+                        if (tkeep && tlast)
+                            state_next = LAST;
+                        else if (!tkeep)
+                            state_next = SEP;
+                end
+            end
+            LAST: begin
+                if (tx_bit_cnt == 3'h7 && clk_div == last_divider)
+                    state_next = SEP; // Go to SEP state after last bit transmitted
+            end
+            SEP: begin
+                if (timeout)
+                    state_next = IDLE; // Go to IDLE after a short separation
+            end
+        endcase
+    end
+
+    // FSM: Output logic
+    always_ff @(posedge clk) begin
+        if (!aresetn) begin
+            tx_shift_reg <= 8'h0;
+            tx_bit_cnt   <= 3'h0;
+            last_divider <= CLK_HI + CLK_LO - 1;
+            tready       <= 1'b0;
+            ssp_clk      <= 1'b0;
+            clk_div      <= 'h0;
+            ssp_csn      <= 1'b1;
+            timer_enable <= 1'b0;
+        end else begin
+            tready       <= 1'b0;
+            ssp_clk      <= 1'b0;
+            ssp_csn      <= 1'b1;
+            
+            clk_div <= clk_div + 1'b1;
+            if (clk_div < last_divider>>1)
+                ssp_clk <= 1'b1;
+            if (clk_div == last_divider) begin
+                ssp_clk <= 1'b1;
+                clk_div <= 'h0;
+            end
+
+            case (state)
+                IDLE: begin
+                    tx_bit_cnt  <= 3'h0;
+                    timer_enable <= 1'b0;
+                    if (clk_div == 0) begin // to eliminate clk glitch when changing divider
+                        if (cfg_divider <= 10 - 1) begin
+                            last_divider <= CLK_HI + CLK_LO - 1;
+                        end else begin
+                            last_divider <= cfg_divider;
+                        end
+                    end
+                    if (tvalid && clk_div == last_divider) begin
+                        tready       <= 1'b1;
+                        if (tkeep) begin
+                            tx_shift_reg <= tdata;
+                            ssp_csn      <= 1'b0;
+                        end
+                    end
+                end
+                TRANSMIT: begin
+                    ssp_csn <= 1'b0;
+
+                    if (clk_div == last_divider) begin
+                        tx_shift_reg <= {tx_shift_reg[6:0], 1'b0}; // Shift left
+                        tx_bit_cnt   <= tx_bit_cnt + 3'h1;
+                        if (tx_bit_cnt == 3'h7) begin
+                            tx_bit_cnt   <= 3'h0;
+                            if (tvalid) begin
+                                tready   <= 1'b1;
+                                if (tkeep) begin
+                                    tx_shift_reg <= tdata; // Load new data if available
+                                end else begin
+                                    ssp_csn <= 1'b1;
+                                    timer_enable <= 1'b1;
+                                end
+                            end
+                        end
+                    end
+                end
+                LAST: begin
+                    ssp_csn <= 1'b0;
+
+                    if (clk_div == last_divider) begin
+                        tx_shift_reg <= {tx_shift_reg[6:0], 1'b0}; // Shift left
+                        tx_bit_cnt   <= tx_bit_cnt + 3'h1;
+                        if (tx_bit_cnt == 3'h7) begin
+                            tx_bit_cnt  <= 3'h0;
+                            ssp_csn     <= 1'b1;
+                            timer_enable <= 1'b1;
+                        end
+                    end
+                end
+                SEP: begin
+                    if (timeout) begin
+                        timer_enable <= 0;
+                    end
+                end
+            endcase
+        end
+    end
+
+    assign ssp_data = tx_shift_reg[7];
+
+    assign ssp_tx_busy = ~ssp_csn;
+
+
+    // Counters for transmitted data and last signals
+    always_ff @(posedge clk) begin
+        if (!aresetn) begin
+            counter_tx_data <= 32'h0;
+            counter_tx_last <= 32'h0;
+        end else begin
+            if (tvalid && tready && tkeep) begin
+                counter_tx_data <= counter_tx_data + 32'h1;
+            end
+            if (tvalid && tready && tlast) begin
+                counter_tx_last <= counter_tx_last + 32'h1;
+            end
+        end
+    end
+
+
+    assign timeout = (timer_us >= min_sep_us) && timer_enable;
+
+    wall_timer #(
+        .MODULE_FREQ_HZ(FREQ_HZ),
+        .US_WIDTH(TIMER_US_WIDTH)
+    ) wall_timer_us_inst (
+        .clk(clk),
+        .rst(!aresetn),
+        .enable(timer_enable),
+        .resume(1'b0),
+        .us(timer_us),
+        .ms(),
+        .sec(),
+        .hour()
+    );
+
+endmodule
--- a/ssp_tx/src/wall_timer.sv
+++ b/ssp_tx/src/wall_timer.sv
@@ -0,0 +1,243 @@
+//---------------------------------------------------------------------------------------
+//    filename: wall_timer.sv
+// description: wall timer
+//      author: leguoqing@paisat.cn
+//---------------------------------------------------------------------------------------
+
+module wall_timer
+#(
+    parameter MODULE_FREQ_HZ    = 50e6,
+    parameter US_WIDTH          = 10,
+    parameter MS_WIDTH          = 0,
+    parameter SEC_WIDTH         = 0,
+    parameter HOUR_WIDTH        = 0
+)(
+    input  logic    clk,
+    input  logic    rst,
+    
+    input  logic    enable,
+    input  logic    resume,
+    output logic    [(US_WIDTH>0 ? US_WIDTH-1 : 0):0] us,
+    output logic    [(MS_WIDTH>0 ? MS_WIDTH-1 : 0):0] ms,
+    output logic    [(SEC_WIDTH>0 ? SEC_WIDTH-1 : 0):0] sec,
+    output logic    [(HOUR_WIDTH>0 ? HOUR_WIDTH-1 : 0):0] hour
+);
+
+    if (MODULE_FREQ_HZ < 1e6) $error("ERROR: MODULE_FREQ_HZ < 1e6!");
+    if (MS_WIDTH > 0 && US_WIDTH < 10) $error("ERROR: MS_WIDTH > 0 && US_WIDTH < 10!");
+    if (SEC_WIDTH > 0 && MS_WIDTH < 10) $error("ERROR: SEC_WIDTH > 0 && MS_WIDTH < 10!");
+    if (HOUR_WIDTH > 0 && SEC_WIDTH < 12) $error("ERROR: HOUR_WIDTH > 0 && SEC_WIDTH < 12!");
+
+    localparam integer FREQ_CLK_MHZ = MODULE_FREQ_HZ / 1e6;
+    localparam integer CYCLE_WIDTH = $clog2(FREQ_CLK_MHZ);
+
+    logic [CYCLE_WIDTH-1:0] cycle_cnt;
+    /* tick signals, better as output port ? */
+    logic us_tick;
+    logic ms_tick;
+    logic sec_tick;
+    logic hour_tick;
+    
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            cycle_cnt <= 0;
+        end else begin
+            if (enable == 1 && resume == 0) begin
+                cycle_cnt <= cycle_cnt + 1;
+                if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
+                    cycle_cnt <= 0;
+                end
+            end else begin
+                cycle_cnt <= 0;
+            end
+        end
+    end
+    
+`ifndef __MICROSATE_SIM__
+    // us
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            us_tick <= 0;
+            us <= 0;
+        end else begin
+            us_tick <= 0;
+            if (enable == 1 && resume == 0) begin
+                if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
+                    us_tick <= 1;
+                end
+                if (us_tick) begin
+                    us <= us + 1;
+                    if (MS_WIDTH == 0) begin
+                        if (us_tick && us != {US_WIDTH{1'b1}}) begin
+                            us <= us + 1;
+                        end
+                    end else begin
+                        if (us_tick) begin
+                            us <= us + 1;
+                            if (us == US_WIDTH'(999)) begin
+                                us <= 0;
+                            end
+                        end
+                    end
+                end
+            end else begin
+                us <= 0;
+            end
+        end
+    end
+
+    // ms
+    generate
+        if (MS_WIDTH > 0) begin
+            always_ff @(posedge clk) begin
+                if (rst) begin
+                    ms_tick <= 0;
+                    ms <= 0;
+                end else begin
+                    ms_tick <= 0;
+                    if (enable == 1 && resume == 0) begin
+                        if (us_tick && us == US_WIDTH'(999)) begin
+                            ms_tick <= 1;
+                        end
+                        if (SEC_WIDTH == 0) begin
+                            if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
+                                ms <= ms + 1;
+                            end
+                        end else begin
+                            if (ms_tick) begin
+                                ms <= ms + 1;
+                                if (ms == MS_WIDTH'(999)) begin
+                                    ms <= 0;
+                                end
+                            end
+                        end
+                    end else begin
+                        ms <= 0;
+                    end
+                end
+            end
+        end else begin
+            assign ms_tick = 0;
+            assign ms = 0;
+        end
+    endgenerate
+`else
+    // us
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            us_tick <= 0;
+            us <= 0;
+        end else begin
+            us_tick <= 0;
+            if (enable == 1 && resume == 0) begin
+                if (cycle_cnt == CYCLE_WIDTH'(FREQ_CLK_MHZ - 1)) begin
+                    us_tick <= 1;
+                end
+            end else begin
+                us <= 0;
+            end
+        end
+    end
+
+    // ms
+    generate
+        if (MS_WIDTH > 0) begin
+            always_ff @(posedge clk) begin
+                if (rst) begin
+                    ms_tick <= 0;
+                    ms <= 0;
+                end else begin
+                    ms_tick <= 0;
+                    if (enable == 1 && resume == 0) begin
+                        if (us_tick) begin
+                            ms_tick <= 1;
+                        end
+                        if (SEC_WIDTH == 0) begin
+                            if (ms_tick && ms != {MS_WIDTH{1'b1}}) begin
+                                ms <= ms + 1;
+                            end
+                        end else begin
+                            if (ms_tick) begin
+                                ms <= ms + 1;
+                                if (ms == MS_WIDTH'(999)) begin
+                                    ms <= 0;
+                                end
+                            end
+                        end
+                    end else begin
+                        ms <= 0;
+                    end
+                end
+            end
+        end else begin
+            assign ms_tick = 0;
+            assign ms = 0;
+        end
+    endgenerate
+`endif
+
+    // sec
+    generate
+        if (SEC_WIDTH > 0) begin
+            always_ff @(posedge clk) begin
+                if (rst) begin
+                    sec_tick <= 0;
+                    sec <= 0;
+                end else begin
+                    sec_tick <= 0;
+                    if (enable == 1 && resume == 0) begin
+                        if (ms_tick && ms == MS_WIDTH'(999)) begin
+                            sec_tick <= 1;
+                        end
+                        if (HOUR_WIDTH == 0) begin
+                            if (sec_tick && sec != {SEC_WIDTH{1'b1}}) begin
+                                sec <= sec + 1;
+                            end
+                        end else begin
+                            if (sec_tick) begin
+                                sec <= sec + 1;
+                                if (sec == SEC_WIDTH'(3599)) begin
+                                    sec <= 0;
+                                end
+                            end
+                        end
+                    end else begin
+                        sec <= 0;
+                    end
+                end
+            end
+        end else begin
+            assign sec_tick = 0;
+            assign sec = 0;
+        end
+    endgenerate
+
+    // hour
+    generate
+        if (HOUR_WIDTH > 0) begin
+            always_ff @(posedge clk) begin
+                if (rst) begin
+                    hour_tick <= 0;
+                    hour <= 0;
+                end else begin
+                    hour_tick <= 0;
+                    if (enable == 1 && resume == 0) begin
+                        if (sec_tick && sec == SEC_WIDTH'(3599)) begin
+                            hour_tick <= 1;
+                        end
+                        if (hour_tick && hour != {HOUR_WIDTH{1'b1}}) begin
+                            hour <= hour + 1;
+                        end
+                    end else begin
+                        hour <= 0;
+                    end
+                end
+            end
+        end else begin
+            assign hour_tick = 0;
+            assign hour = 0;
+        end
+    endgenerate
+
+
+endmodule
--- a/ssp_tx/src/xgui/ssp_tx_v1_0.tcl
+++ b/ssp_tx/src/xgui/ssp_tx_v1_0.tcl
@@ -0,0 +1,40 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "FREQ_HZ" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "SSP_HZ" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
+	# Procedure called to update FREQ_HZ when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FREQ_HZ { PARAM_VALUE.FREQ_HZ } {
+	# Procedure called to validate FREQ_HZ
+	return true
+}
+
+proc update_PARAM_VALUE.SSP_HZ { PARAM_VALUE.SSP_HZ } {
+	# Procedure called to update SSP_HZ when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SSP_HZ { PARAM_VALUE.SSP_HZ } {
+	# Procedure called to validate SSP_HZ
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.FREQ_HZ { MODELPARAM_VALUE.FREQ_HZ PARAM_VALUE.FREQ_HZ } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FREQ_HZ}] ${MODELPARAM_VALUE.FREQ_HZ}
+}
+
+proc update_MODELPARAM_VALUE.SSP_HZ { MODELPARAM_VALUE.SSP_HZ PARAM_VALUE.SSP_HZ } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SSP_HZ}] ${MODELPARAM_VALUE.SSP_HZ}
+}
+