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ssp_rx/src/ssp_rx.sv
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322
ssp_rx/src/ssp_rx.sv
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//---------------------------------------------------------------------------------------
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// filename: ssp_rx.sv
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// description: synchronous serial peripheral interface receiver
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// author: leguoqing@paisat.cn
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//---------------------------------------------------------------------------------------
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module ssp_rx #(
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parameter integer FREQ_HZ = 100e6,
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parameter integer SSP_HZ = 10e6,
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parameter integer STREAM_WIDTH = 8
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) (
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input logic clk,
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input logic aresetn,
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input logic enable,
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output logic [STREAM_WIDTH-1:0] tdata,
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output logic tvalid,
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output logic tkeep,
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output logic tstrb,
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output logic tlast,
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input logic tready,
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input logic ssp_clk,
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input logic ssp_csn,
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input logic ssp_data,
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input logic [31:0] config_00,
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input logic [31:0] config_01,
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input logic [31:0] config_02,
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output logic [31:0] status_00,
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output logic [31:0] status_01,
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output logic [31:0] status_02,
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output logic [31:0] status_03,
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output logic [31:0] status_04,
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output logic [31:0] status_05,
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output logic [31:0] status_06,
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output logic [31:0] status_07
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);
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if ($ceil(FREQ_HZ/SSP_HZ) != $floor(FREQ_HZ/SSP_HZ)) begin
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$fatal("%m: FREQ_HZ must be an integer multiple of SSP_HZ!");
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end else if (FREQ_HZ/SSP_HZ < 6) begin
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$fatal("%m: FREQ_HZ/SSP_HZ < 6!");
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end else if ((FREQ_HZ/SSP_HZ)%2 != 0) begin
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$warning("%m: FREQ_HZ/SSP_HZ is not an even number, which means the SSP clock will be asymmetric!");
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end
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localparam integer CLK_HI = $ceil(FREQ_HZ/(2*SSP_HZ));
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localparam integer CLK_LO = $floor(FREQ_HZ/(2*SSP_HZ));
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// State encoding
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typedef enum logic [1:0] {
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IDLE,
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RECEIVE,
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LAST
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} state_t;
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state_t state, state_next;
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logic [ 7:0] fsm_hardcode;
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logic [31:0] counter_rx_data;
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logic [31:0] counter_rx_last;
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logic [31:0] counter_half_beats;
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logic [31:0] counter_clk_falling;
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logic [31:0] counter_data_rising;
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logic [31:0] counter_csn_falling;
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logic [31:0] counter_csn_rising;
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logic mode_wire3;
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logic mode_wire2;
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logic [3:0] header_size;
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logic [15:0] frame_size;
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logic [31:0] frame_header;
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logic [31:0] frame_header_mask;
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logic cfg_valid;
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logic [31:0] frame_header_candidate;
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logic header_matched;
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logic [31:0] header_mask_shifted;
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logic [15:0] beats_cnt;
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logic [STREAM_WIDTH-1:0] rx_shift_reg;
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logic [$clog2(STREAM_WIDTH)-1:0] rx_bit_cnt;
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logic data_valid;
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logic [STREAM_WIDTH-1:0] data;
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logic [2:0] ssp_csn_sync;
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logic [2:0] ssp_data_sync;
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logic [2:0] ssp_clk_sync;
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logic ssp_clk_falling;
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assign mode_wire3 = config_00[0];
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assign mode_wire2 = config_00[1];
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assign header_size = config_00[8 +: 4];
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assign frame_size = config_00[16 +: 16];
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assign frame_header = config_01;
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assign frame_header_mask = config_02;
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assign cfg_valid = (mode_wire3 && !mode_wire2) || (!mode_wire3 && mode_wire2 && header_size != 0 && frame_size != 0 && frame_header_mask != 0 && frame_header != 0);
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assign status_00 = {8'(cfg_valid), 5'h0, ssp_clk_sync[2], ssp_csn_sync[2], ssp_data_sync[2], fsm_hardcode, 8'(enable)};
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assign status_01 = counter_rx_data;
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assign status_02 = counter_rx_last;
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assign status_03 = counter_half_beats;
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assign status_04 = counter_clk_falling;
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assign status_05 = counter_data_rising;
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assign status_06 = counter_csn_falling;
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assign status_07 = counter_csn_rising;
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// synchronize ssp_clk/ssp_csn/ssp_data to clk domain
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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ssp_csn_sync <= 3'b111;
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ssp_data_sync <= 3'b000;
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ssp_clk_sync <= 3'b000;
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end else begin
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ssp_csn_sync <= {ssp_csn_sync[1:0], ssp_csn};
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ssp_data_sync <= {ssp_data_sync[1:0], ssp_data};
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ssp_clk_sync <= {ssp_clk_sync[1:0], ssp_clk};
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end
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end
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assign ssp_clk_falling = (ssp_clk_sync[2:1] == 2'b10);
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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counter_clk_falling <= 32'h0;
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counter_data_rising <= 32'h0;
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counter_csn_falling <= 32'h0;
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counter_csn_rising <= 32'h0;
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end else begin
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if (ssp_clk_falling) begin
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counter_clk_falling <= counter_clk_falling + 32'h1;
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end
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if (ssp_data_sync[2:1] == 2'b01) begin
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counter_data_rising <= counter_data_rising + 32'h1;
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end
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if (ssp_csn_sync[2:1] == 2'b10) begin
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counter_csn_falling <= counter_csn_falling + 32'h1;
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end
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if (ssp_csn_sync[2:1] == 2'b01) begin
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counter_csn_rising <= counter_csn_rising + 32'h1;
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end
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end
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end
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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fsm_hardcode <= 8'h0;
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end else begin
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case (state)
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IDLE:
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fsm_hardcode <= 8'h0;
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RECEIVE:
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fsm_hardcode <= 8'h1;
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LAST:
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fsm_hardcode <= 8'h2;
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default:
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fsm_hardcode <= 8'hF;
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endcase
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end
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end
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// FSM: State register
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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state <= IDLE;
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end else begin
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state <= state_next;
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end
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end
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// FSM: Next state logic
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always_comb begin
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state_next = state;
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case (state)
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IDLE: begin
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if (cfg_valid)
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if (mode_wire3) begin
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if (!ssp_csn_sync[1]) begin
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state_next = RECEIVE;
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end
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end else if (mode_wire2) begin
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state_next = RECEIVE;
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end
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end
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RECEIVE: begin
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if (mode_wire3) begin
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if (ssp_csn_sync[1]) begin
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state_next = LAST;
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end
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end else if (mode_wire2) begin
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if (header_matched && |frame_size != 0 && beats_cnt == frame_size) begin
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state_next = LAST;
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end
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end
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if (!cfg_valid) begin
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state_next = IDLE;
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end
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end
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LAST: begin
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state_next = IDLE;
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end
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endcase
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end
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// FSM: Output logic
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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rx_shift_reg <= 0;
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rx_bit_cnt <= 0;
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data_valid <= 0;
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data <= 0;
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tvalid <= 0;
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tstrb <= 0;
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tkeep <= 0;
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tlast <= 0;
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tdata <= 0;
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header_matched <= 0;
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frame_header_candidate <= 0;
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beats_cnt <= 0;
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header_mask_shifted <= 0;
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end else begin
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if (tready) begin
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tvalid <= 1'b0;
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tstrb <= 1'b0;
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tkeep <= 1'b0;
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tlast <= 1'b0;
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end
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case (state)
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IDLE: begin
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rx_shift_reg <= 0;
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rx_bit_cnt <= 0;
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data_valid <= 0;
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data <= 0;
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header_matched <= 0;
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frame_header_candidate <= 0;
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beats_cnt <= 0;
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header_mask_shifted <= 0;
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end
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RECEIVE: begin
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if (ssp_clk_falling) begin
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rx_shift_reg <= {rx_shift_reg[STREAM_WIDTH-2:0], ssp_data_sync[1]};
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rx_bit_cnt <= rx_bit_cnt + 1'b1;
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if (mode_wire3 == 1 || (mode_wire2 == 1 && header_matched)) begin
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if (rx_bit_cnt == STREAM_WIDTH-1) begin
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rx_bit_cnt <= 0;
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if (mode_wire3 == 0)
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beats_cnt <= beats_cnt + 1'b1;
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data <= {rx_shift_reg[STREAM_WIDTH-2:0], ssp_data_sync[1]};
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data_valid <= 1'b1; // defer one beat
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if (data_valid) begin
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tvalid <= 1'b1;
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tstrb <= 1'b1;
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tkeep <= 1'b1;
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tlast <= 1'b0;
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tdata <= data;
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end
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end
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end
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if (mode_wire3 == 0 && mode_wire2 == 1 && header_matched == 0) begin
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frame_header_candidate <= {frame_header_candidate[30:0], ssp_data_sync[1]};
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end
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end
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if (mode_wire3 == 0 && mode_wire2 == 1 && frame_header_candidate == (frame_header & frame_header_mask)) begin
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header_matched <= 1'b1;
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rx_bit_cnt <= 0;
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header_mask_shifted <= frame_header_mask;
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end
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// implicitly condition: has enough cycle to accomplish before next beat arrives
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if (header_matched && beats_cnt < header_size) begin
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tvalid <= 1'b1;
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tstrb <= 1'b1;
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tkeep <= |header_mask_shifted[32-STREAM_WIDTH+:STREAM_WIDTH];
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tlast <= 1'b0;
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tdata <= frame_header_candidate[32-STREAM_WIDTH+:STREAM_WIDTH];
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if (tvalid && tready) begin
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tvalid <= 1'b0;
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tstrb <= 1'b0;
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tkeep <= 1'b0;
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tlast <= 1'b0;
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frame_header_candidate <= {frame_header_candidate[0+:32-STREAM_WIDTH], {STREAM_WIDTH{1'b0}}};
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header_mask_shifted <= {header_mask_shifted[0+:32-STREAM_WIDTH], {STREAM_WIDTH{1'b0}}};
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beats_cnt <= beats_cnt + |header_mask_shifted[32-STREAM_WIDTH+:STREAM_WIDTH];
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end
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end
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end
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LAST: begin
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tvalid <= 1'b1;
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tstrb <= 1'b1;
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tkeep <= 1'b1;
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tlast <= 1'b1;
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tdata <= data;
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end
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (!aresetn) begin
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counter_rx_data <= 32'h0;
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counter_rx_last <= 32'h0;
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counter_half_beats <= 0;
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end else begin
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if (tvalid && tready && tkeep) begin
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counter_rx_data <= counter_rx_data + 32'h1;
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end
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if (tvalid && tready && tlast) begin
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counter_rx_last <= counter_rx_last + 32'h1;
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end
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if (mode_wire3 == 1 && ssp_csn_sync[1] && state == RECEIVE && rx_bit_cnt != 3'h0) begin
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counter_half_beats <= counter_half_beats + 32'h1;
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end
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end
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end
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endmodule
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