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ssp_combo/component.xml
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ssp_combo/component.xml
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ssp_combo/sim/ssp_combo.v
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ssp_combo/sim/ssp_combo.v
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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//Date : Mon Feb 2 19:53:39 2026
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//Host : le-ThinkStation running 64-bit major release (build 9200)
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//Command : generate_target ssp_combo.bd
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//Design : ssp_combo
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* CORE_GENERATION_INFO = "ssp_combo,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ssp_combo,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "ssp_combo.hwdef" *)
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module ssp_combo
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(M_AXI_MM2S_araddr,
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M_AXI_MM2S_arburst,
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M_AXI_MM2S_arcache,
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M_AXI_MM2S_arid,
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M_AXI_MM2S_arlen,
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M_AXI_MM2S_arprot,
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M_AXI_MM2S_arready,
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M_AXI_MM2S_arsize,
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M_AXI_MM2S_aruser,
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M_AXI_MM2S_arvalid,
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M_AXI_MM2S_rdata,
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M_AXI_MM2S_rlast,
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M_AXI_MM2S_rready,
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M_AXI_MM2S_rresp,
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M_AXI_MM2S_rvalid,
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M_AXI_S2MM_awaddr,
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M_AXI_S2MM_awburst,
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M_AXI_S2MM_awcache,
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M_AXI_S2MM_awid,
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M_AXI_S2MM_awlen,
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M_AXI_S2MM_awprot,
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M_AXI_S2MM_awready,
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M_AXI_S2MM_awsize,
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M_AXI_S2MM_awuser,
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M_AXI_S2MM_awvalid,
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M_AXI_S2MM_bready,
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M_AXI_S2MM_bresp,
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M_AXI_S2MM_bvalid,
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M_AXI_S2MM_wdata,
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M_AXI_S2MM_wlast,
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M_AXI_S2MM_wready,
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M_AXI_S2MM_wstrb,
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M_AXI_S2MM_wvalid,
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S_AXI_TXDESC_araddr,
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S_AXI_TXDESC_arburst,
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S_AXI_TXDESC_arcache,
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S_AXI_TXDESC_arlen,
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S_AXI_TXDESC_arlock,
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S_AXI_TXDESC_arprot,
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S_AXI_TXDESC_arready,
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S_AXI_TXDESC_arsize,
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S_AXI_TXDESC_arvalid,
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S_AXI_TXDESC_awaddr,
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S_AXI_TXDESC_awburst,
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S_AXI_TXDESC_awcache,
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S_AXI_TXDESC_awlen,
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S_AXI_TXDESC_awlock,
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S_AXI_TXDESC_awprot,
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S_AXI_TXDESC_awready,
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S_AXI_TXDESC_awsize,
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S_AXI_TXDESC_awvalid,
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S_AXI_TXDESC_bready,
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S_AXI_TXDESC_bresp,
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S_AXI_TXDESC_bvalid,
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S_AXI_TXDESC_rdata,
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S_AXI_TXDESC_rlast,
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S_AXI_TXDESC_rready,
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S_AXI_TXDESC_rresp,
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S_AXI_TXDESC_rvalid,
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S_AXI_TXDESC_wdata,
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S_AXI_TXDESC_wlast,
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S_AXI_TXDESC_wready,
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S_AXI_TXDESC_wstrb,
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S_AXI_TXDESC_wvalid,
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aresetn,
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clk,
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s_axil_rx_araddr,
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s_axil_rx_arprot,
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s_axil_rx_arready,
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s_axil_rx_arvalid,
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s_axil_rx_awaddr,
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s_axil_rx_awprot,
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s_axil_rx_awready,
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s_axil_rx_awvalid,
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s_axil_rx_bready,
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s_axil_rx_bresp,
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s_axil_rx_bvalid,
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s_axil_rx_rdata,
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s_axil_rx_rready,
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s_axil_rx_rresp,
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s_axil_rx_rvalid,
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s_axil_rx_wdata,
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s_axil_rx_wready,
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s_axil_rx_wstrb,
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s_axil_rx_wvalid,
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s_axil_tx_araddr,
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s_axil_tx_arprot,
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s_axil_tx_arready,
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s_axil_tx_arvalid,
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s_axil_tx_awaddr,
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s_axil_tx_awprot,
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s_axil_tx_awready,
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s_axil_tx_awvalid,
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s_axil_tx_bready,
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s_axil_tx_bresp,
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s_axil_tx_bvalid,
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s_axil_tx_rdata,
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s_axil_tx_rready,
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s_axil_tx_rresp,
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s_axil_tx_rvalid,
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s_axil_tx_wdata,
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s_axil_tx_wready,
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s_axil_tx_wstrb,
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s_axil_tx_wvalid,
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ssp_rx_clk,
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ssp_rx_csn,
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ssp_rx_data,
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ssp_tx_clk,
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ssp_tx_csn,
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ssp_tx_data);
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_MM2S, ADDR_WIDTH 32, ARUSER_WIDTH 4, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 0, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 0, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_MM2S_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST" *) output [1:0]M_AXI_MM2S_arburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE" *) output [3:0]M_AXI_MM2S_arcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID" *) output [3:0]M_AXI_MM2S_arid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]M_AXI_MM2S_arlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT" *) output [2:0]M_AXI_MM2S_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY" *) input M_AXI_MM2S_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]M_AXI_MM2S_arsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER" *) output [3:0]M_AXI_MM2S_aruser;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID" *) output M_AXI_MM2S_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA" *) input [127:0]M_AXI_MM2S_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST" *) input M_AXI_MM2S_rlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY" *) output M_AXI_MM2S_rready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP" *) input [1:0]M_AXI_MM2S_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID" *) input M_AXI_MM2S_rvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_S2MM, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 4, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 0, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE WRITE_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_S2MM_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST" *) output [1:0]M_AXI_S2MM_awburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE" *) output [3:0]M_AXI_S2MM_awcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID" *) output [3:0]M_AXI_S2MM_awid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN" *) output [7:0]M_AXI_S2MM_awlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT" *) output [2:0]M_AXI_S2MM_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY" *) input M_AXI_S2MM_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE" *) output [2:0]M_AXI_S2MM_awsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER" *) output [3:0]M_AXI_S2MM_awuser;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID" *) output M_AXI_S2MM_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY" *) output M_AXI_S2MM_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP" *) input [1:0]M_AXI_S2MM_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID" *) input M_AXI_S2MM_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA" *) output [127:0]M_AXI_S2MM_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST" *) output M_AXI_S2MM_wlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY" *) input M_AXI_S2MM_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB" *) output [15:0]M_AXI_S2MM_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID" *) output M_AXI_S2MM_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_TXDESC, ADDR_WIDTH 15, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 64, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [14:0]S_AXI_TXDESC_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARBURST" *) input [1:0]S_AXI_TXDESC_arburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARCACHE" *) input [3:0]S_AXI_TXDESC_arcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLEN" *) input [7:0]S_AXI_TXDESC_arlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLOCK" *) input S_AXI_TXDESC_arlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARPROT" *) input [2:0]S_AXI_TXDESC_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARREADY" *) output S_AXI_TXDESC_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARSIZE" *) input [2:0]S_AXI_TXDESC_arsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARVALID" *) input S_AXI_TXDESC_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWADDR" *) input [14:0]S_AXI_TXDESC_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWBURST" *) input [1:0]S_AXI_TXDESC_awburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWCACHE" *) input [3:0]S_AXI_TXDESC_awcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLEN" *) input [7:0]S_AXI_TXDESC_awlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLOCK" *) input S_AXI_TXDESC_awlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWPROT" *) input [2:0]S_AXI_TXDESC_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWREADY" *) output S_AXI_TXDESC_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWSIZE" *) input [2:0]S_AXI_TXDESC_awsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWVALID" *) input S_AXI_TXDESC_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BREADY" *) input S_AXI_TXDESC_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BRESP" *) output [1:0]S_AXI_TXDESC_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BVALID" *) output S_AXI_TXDESC_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RDATA" *) output [63:0]S_AXI_TXDESC_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RLAST" *) output S_AXI_TXDESC_rlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RREADY" *) input S_AXI_TXDESC_rready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RRESP" *) output [1:0]S_AXI_TXDESC_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RVALID" *) output S_AXI_TXDESC_rvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WDATA" *) input [63:0]S_AXI_TXDESC_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WLAST" *) input S_AXI_TXDESC_wlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WREADY" *) output S_AXI_TXDESC_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WSTRB" *) input [7:0]S_AXI_TXDESC_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WVALID" *) input S_AXI_TXDESC_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input aresetn;
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXI_S2MM:s_axil_rx:s_axil_tx:S_AXI_TXDESC, ASSOCIATED_RESET aresetn, CLK_DOMAIN ssp_combo_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0" *) input clk;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_rx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_rx_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARPROT" *) input [2:0]s_axil_rx_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARREADY" *) output s_axil_rx_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARVALID" *) input s_axil_rx_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWADDR" *) input [31:0]s_axil_rx_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWPROT" *) input [2:0]s_axil_rx_awprot;
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||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWREADY" *) output s_axil_rx_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWVALID" *) input s_axil_rx_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BREADY" *) input s_axil_rx_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BRESP" *) output [1:0]s_axil_rx_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BVALID" *) output s_axil_rx_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RDATA" *) output [31:0]s_axil_rx_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RREADY" *) input s_axil_rx_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RRESP" *) output [1:0]s_axil_rx_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RVALID" *) output s_axil_rx_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WDATA" *) input [31:0]s_axil_rx_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WREADY" *) output s_axil_rx_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WSTRB" *) input [3:0]s_axil_rx_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WVALID" *) input s_axil_rx_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_tx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_tx_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARPROT" *) input [2:0]s_axil_tx_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARREADY" *) output s_axil_tx_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARVALID" *) input s_axil_tx_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWADDR" *) input [31:0]s_axil_tx_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWPROT" *) input [2:0]s_axil_tx_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWREADY" *) output s_axil_tx_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWVALID" *) input s_axil_tx_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BREADY" *) input s_axil_tx_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BRESP" *) output [1:0]s_axil_tx_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BVALID" *) output s_axil_tx_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RDATA" *) output [31:0]s_axil_tx_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RREADY" *) input s_axil_tx_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RRESP" *) output [1:0]s_axil_tx_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RVALID" *) output s_axil_tx_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WDATA" *) input [31:0]s_axil_tx_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WREADY" *) output s_axil_tx_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WSTRB" *) input [3:0]s_axil_tx_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WVALID" *) input s_axil_tx_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_RX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_RX_CLK, CLK_DOMAIN ssp_combo_ssp_rx_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input ssp_rx_clk;
|
||||
input ssp_rx_csn;
|
||||
input ssp_rx_data;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_TX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_TX_CLK, CLK_DOMAIN ssp_combo_ssp_tx_0_0_ssp_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) output ssp_tx_clk;
|
||||
output ssp_tx_csn;
|
||||
output ssp_tx_data;
|
||||
|
||||
wire [14:0]S_AXI_0_1_ARADDR;
|
||||
wire [1:0]S_AXI_0_1_ARBURST;
|
||||
wire [3:0]S_AXI_0_1_ARCACHE;
|
||||
wire [7:0]S_AXI_0_1_ARLEN;
|
||||
wire S_AXI_0_1_ARLOCK;
|
||||
wire [2:0]S_AXI_0_1_ARPROT;
|
||||
wire S_AXI_0_1_ARREADY;
|
||||
wire [2:0]S_AXI_0_1_ARSIZE;
|
||||
wire S_AXI_0_1_ARVALID;
|
||||
wire [14:0]S_AXI_0_1_AWADDR;
|
||||
wire [1:0]S_AXI_0_1_AWBURST;
|
||||
wire [3:0]S_AXI_0_1_AWCACHE;
|
||||
wire [7:0]S_AXI_0_1_AWLEN;
|
||||
wire S_AXI_0_1_AWLOCK;
|
||||
wire [2:0]S_AXI_0_1_AWPROT;
|
||||
wire S_AXI_0_1_AWREADY;
|
||||
wire [2:0]S_AXI_0_1_AWSIZE;
|
||||
wire S_AXI_0_1_AWVALID;
|
||||
wire S_AXI_0_1_BREADY;
|
||||
wire [1:0]S_AXI_0_1_BRESP;
|
||||
wire S_AXI_0_1_BVALID;
|
||||
wire [63:0]S_AXI_0_1_RDATA;
|
||||
wire S_AXI_0_1_RLAST;
|
||||
wire S_AXI_0_1_RREADY;
|
||||
wire [1:0]S_AXI_0_1_RRESP;
|
||||
wire S_AXI_0_1_RVALID;
|
||||
wire [63:0]S_AXI_0_1_WDATA;
|
||||
wire S_AXI_0_1_WLAST;
|
||||
wire S_AXI_0_1_WREADY;
|
||||
wire [7:0]S_AXI_0_1_WSTRB;
|
||||
wire S_AXI_0_1_WVALID;
|
||||
wire aclk_0_1;
|
||||
wire aresetn_0_1;
|
||||
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
|
||||
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
|
||||
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
|
||||
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
|
||||
wire [7:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
|
||||
wire [14:0]axi_bram_ctrl_0_bram_addr_a;
|
||||
wire [7:0]axi_datamover_0_M_AXIS_MM2S_STS_TDATA;
|
||||
wire [0:0]axi_datamover_0_M_AXIS_MM2S_STS_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TVALID;
|
||||
wire [7:0]axi_datamover_0_M_AXIS_MM2S_TDATA;
|
||||
wire [0:0]axi_datamover_0_M_AXIS_MM2S_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXIS_S2MM_STS_TDATA;
|
||||
wire [3:0]axi_datamover_0_M_AXIS_S2MM_STS_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXI_MM2S_ARADDR;
|
||||
wire [1:0]axi_datamover_0_M_AXI_MM2S_ARBURST;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARCACHE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARID;
|
||||
wire [7:0]axi_datamover_0_M_AXI_MM2S_ARLEN;
|
||||
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARPROT;
|
||||
wire axi_datamover_0_M_AXI_MM2S_ARREADY;
|
||||
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARSIZE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARUSER;
|
||||
wire axi_datamover_0_M_AXI_MM2S_ARVALID;
|
||||
wire [127:0]axi_datamover_0_M_AXI_MM2S_RDATA;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RLAST;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RREADY;
|
||||
wire [1:0]axi_datamover_0_M_AXI_MM2S_RRESP;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXI_S2MM_AWADDR;
|
||||
wire [1:0]axi_datamover_0_M_AXI_S2MM_AWBURST;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWCACHE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWID;
|
||||
wire [7:0]axi_datamover_0_M_AXI_S2MM_AWLEN;
|
||||
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWPROT;
|
||||
wire axi_datamover_0_M_AXI_S2MM_AWREADY;
|
||||
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWSIZE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWUSER;
|
||||
wire axi_datamover_0_M_AXI_S2MM_AWVALID;
|
||||
wire axi_datamover_0_M_AXI_S2MM_BREADY;
|
||||
wire [1:0]axi_datamover_0_M_AXI_S2MM_BRESP;
|
||||
wire axi_datamover_0_M_AXI_S2MM_BVALID;
|
||||
wire [127:0]axi_datamover_0_M_AXI_S2MM_WDATA;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WLAST;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WREADY;
|
||||
wire [15:0]axi_datamover_0_M_AXI_S2MM_WSTRB;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WVALID;
|
||||
wire axi_datamover_0_mm2s_err;
|
||||
wire axi_datamover_0_s2mm_err;
|
||||
wire [31:0]axil_reg_if_0_reg_rd_addr;
|
||||
wire axil_reg_if_0_reg_rd_en;
|
||||
wire [31:0]axil_reg_if_0_reg_wr_addr;
|
||||
wire [31:0]axil_reg_if_0_reg_wr_data;
|
||||
wire axil_reg_if_0_reg_wr_en;
|
||||
wire [3:0]axil_reg_if_0_reg_wr_strb;
|
||||
wire [31:0]axil_reg_if_1_reg_rd_addr;
|
||||
wire axil_reg_if_1_reg_rd_en;
|
||||
wire [31:0]axil_reg_if_1_reg_wr_addr;
|
||||
wire [31:0]axil_reg_if_1_reg_wr_data;
|
||||
wire axil_reg_if_1_reg_wr_en;
|
||||
wire [3:0]axil_reg_if_1_reg_wr_strb;
|
||||
wire [7:0]axis_data_fifo_0_M_AXIS_TDATA;
|
||||
wire [0:0]axis_data_fifo_0_M_AXIS_TKEEP;
|
||||
wire axis_data_fifo_0_M_AXIS_TLAST;
|
||||
wire axis_data_fifo_0_M_AXIS_TREADY;
|
||||
wire axis_data_fifo_0_M_AXIS_TVALID;
|
||||
wire [7:0]axis_data_fifo_1_M_AXIS_TDATA;
|
||||
wire [0:0]axis_data_fifo_1_M_AXIS_TKEEP;
|
||||
wire axis_data_fifo_1_M_AXIS_TLAST;
|
||||
wire axis_data_fifo_1_M_AXIS_TREADY;
|
||||
wire axis_data_fifo_1_M_AXIS_TVALID;
|
||||
wire [31:0]regfile_0_reg_0;
|
||||
wire [31:0]regfile_0_reg_1;
|
||||
wire [31:0]regfile_0_reg_2;
|
||||
wire [31:0]regfile_0_reg_3;
|
||||
wire [31:0]regfile_0_reg_4;
|
||||
wire [31:0]regfile_0_reg_5;
|
||||
wire [31:0]regfile_0_reg_6;
|
||||
wire regfile_0_reg_rd_ack;
|
||||
wire [31:0]regfile_0_reg_rd_data;
|
||||
wire regfile_0_reg_rd_wait;
|
||||
wire regfile_0_reg_wr_ack;
|
||||
wire regfile_0_reg_wr_wait;
|
||||
wire [31:0]regfile_1_reg_0;
|
||||
wire [31:0]regfile_1_reg_1;
|
||||
wire [31:0]regfile_1_reg_2;
|
||||
wire [31:0]regfile_1_reg_3;
|
||||
wire [31:0]regfile_1_reg_4;
|
||||
wire regfile_1_reg_rd_ack;
|
||||
wire [31:0]regfile_1_reg_rd_data;
|
||||
wire regfile_1_reg_rd_wait;
|
||||
wire regfile_1_reg_wr_ack;
|
||||
wire regfile_1_reg_wr_wait;
|
||||
wire [31:0]s_axil_0_1_ARADDR;
|
||||
wire [2:0]s_axil_0_1_ARPROT;
|
||||
wire s_axil_0_1_ARREADY;
|
||||
wire s_axil_0_1_ARVALID;
|
||||
wire [31:0]s_axil_0_1_AWADDR;
|
||||
wire [2:0]s_axil_0_1_AWPROT;
|
||||
wire s_axil_0_1_AWREADY;
|
||||
wire s_axil_0_1_AWVALID;
|
||||
wire s_axil_0_1_BREADY;
|
||||
wire [1:0]s_axil_0_1_BRESP;
|
||||
wire s_axil_0_1_BVALID;
|
||||
wire [31:0]s_axil_0_1_RDATA;
|
||||
wire s_axil_0_1_RREADY;
|
||||
wire [1:0]s_axil_0_1_RRESP;
|
||||
wire s_axil_0_1_RVALID;
|
||||
wire [31:0]s_axil_0_1_WDATA;
|
||||
wire s_axil_0_1_WREADY;
|
||||
wire [3:0]s_axil_0_1_WSTRB;
|
||||
wire s_axil_0_1_WVALID;
|
||||
wire [31:0]s_axil_0_2_ARADDR;
|
||||
wire [2:0]s_axil_0_2_ARPROT;
|
||||
wire s_axil_0_2_ARREADY;
|
||||
wire s_axil_0_2_ARVALID;
|
||||
wire [31:0]s_axil_0_2_AWADDR;
|
||||
wire [2:0]s_axil_0_2_AWPROT;
|
||||
wire s_axil_0_2_AWREADY;
|
||||
wire s_axil_0_2_AWVALID;
|
||||
wire s_axil_0_2_BREADY;
|
||||
wire [1:0]s_axil_0_2_BRESP;
|
||||
wire s_axil_0_2_BVALID;
|
||||
wire [31:0]s_axil_0_2_RDATA;
|
||||
wire s_axil_0_2_RREADY;
|
||||
wire [1:0]s_axil_0_2_RRESP;
|
||||
wire s_axil_0_2_RVALID;
|
||||
wire [31:0]s_axil_0_2_WDATA;
|
||||
wire s_axil_0_2_WREADY;
|
||||
wire [3:0]s_axil_0_2_WSTRB;
|
||||
wire s_axil_0_2_WVALID;
|
||||
wire ssp_clk_0_1;
|
||||
wire ssp_csn_0_1;
|
||||
wire ssp_data_0_1;
|
||||
wire [7:0]ssp_rx_0_interface_axis_TDATA;
|
||||
wire ssp_rx_0_interface_axis_TKEEP;
|
||||
wire ssp_rx_0_interface_axis_TLAST;
|
||||
wire ssp_rx_0_interface_axis_TREADY;
|
||||
wire ssp_rx_0_interface_axis_TSTRB;
|
||||
wire ssp_rx_0_interface_axis_TVALID;
|
||||
wire [31:0]ssp_rx_0_status_00;
|
||||
wire [31:0]ssp_rx_0_status_01;
|
||||
wire [31:0]ssp_rx_0_status_02;
|
||||
wire [31:0]ssp_rx_0_status_03;
|
||||
wire [31:0]ssp_rx_0_status_04;
|
||||
wire [31:0]ssp_rx_0_status_05;
|
||||
wire [31:0]ssp_rx_0_status_06;
|
||||
wire [31:0]ssp_rx_0_status_07;
|
||||
wire ssp_tx_0_ssp_clk;
|
||||
wire ssp_tx_0_ssp_csn;
|
||||
wire ssp_tx_0_ssp_data;
|
||||
wire [31:0]ssp_tx_0_status;
|
||||
wire [31:0]ssp_tx_0_status_00;
|
||||
wire [31:0]ssp_tx_0_status_01;
|
||||
wire [31:0]ssp_tx_0_status_02;
|
||||
wire [31:0]ssp_tx_0_tx_data_count;
|
||||
wire [31:0]ssp_tx_0_tx_last_count;
|
||||
wire [71:0]stream_rx_ctrl_0_cmd_TDATA;
|
||||
wire stream_rx_ctrl_0_cmd_TREADY;
|
||||
wire stream_rx_ctrl_0_cmd_TVALID;
|
||||
wire [7:0]stream_rx_ctrl_0_egress_TDATA;
|
||||
wire [0:0]stream_rx_ctrl_0_egress_TKEEP;
|
||||
wire stream_rx_ctrl_0_egress_TLAST;
|
||||
wire stream_rx_ctrl_0_egress_TREADY;
|
||||
wire [0:0]stream_rx_ctrl_0_egress_TSTRB;
|
||||
wire stream_rx_ctrl_0_egress_TVALID;
|
||||
wire stream_rx_ctrl_0_enable;
|
||||
wire stream_rx_ctrl_0_s2mm_resetn;
|
||||
wire [31:0]stream_rx_ctrl_0_status_00;
|
||||
wire [31:0]stream_rx_ctrl_0_status_01;
|
||||
wire [31:0]stream_rx_ctrl_0_status_02;
|
||||
wire [31:0]stream_rx_ctrl_0_status_03;
|
||||
wire [31:0]stream_rx_ctrl_0_status_04;
|
||||
wire [31:0]stream_rx_ctrl_0_status_05;
|
||||
wire [31:0]stream_rx_ctrl_0_status_06;
|
||||
wire [31:0]stream_rx_ctrl_0_status_07;
|
||||
wire [71:0]stream_tx_ctrl_0_cmd_TDATA;
|
||||
wire stream_tx_ctrl_0_cmd_TREADY;
|
||||
wire stream_tx_ctrl_0_cmd_TVALID;
|
||||
wire [10:0]stream_tx_ctrl_0_desc_if_ADDR;
|
||||
wire stream_tx_ctrl_0_desc_if_CLK;
|
||||
wire [63:0]stream_tx_ctrl_0_desc_if_DIN;
|
||||
wire [63:0]stream_tx_ctrl_0_desc_if_DOUT;
|
||||
wire [7:0]stream_tx_ctrl_0_desc_if_WE;
|
||||
wire [31:0]stream_tx_ctrl_0_status_00;
|
||||
wire [31:0]stream_tx_ctrl_0_status_01;
|
||||
wire [31:0]stream_tx_ctrl_0_status_02;
|
||||
wire [31:0]stream_tx_ctrl_0_status_03;
|
||||
wire [31:0]stream_tx_ctrl_0_status_04;
|
||||
wire [10:0]xlslice_0_Dout;
|
||||
|
||||
assign M_AXI_MM2S_araddr[31:0] = axi_datamover_0_M_AXI_MM2S_ARADDR;
|
||||
assign M_AXI_MM2S_arburst[1:0] = axi_datamover_0_M_AXI_MM2S_ARBURST;
|
||||
assign M_AXI_MM2S_arcache[3:0] = axi_datamover_0_M_AXI_MM2S_ARCACHE;
|
||||
assign M_AXI_MM2S_arid[3:0] = axi_datamover_0_M_AXI_MM2S_ARID;
|
||||
assign M_AXI_MM2S_arlen[7:0] = axi_datamover_0_M_AXI_MM2S_ARLEN;
|
||||
assign M_AXI_MM2S_arprot[2:0] = axi_datamover_0_M_AXI_MM2S_ARPROT;
|
||||
assign M_AXI_MM2S_arsize[2:0] = axi_datamover_0_M_AXI_MM2S_ARSIZE;
|
||||
assign M_AXI_MM2S_aruser[3:0] = axi_datamover_0_M_AXI_MM2S_ARUSER;
|
||||
assign M_AXI_MM2S_arvalid = axi_datamover_0_M_AXI_MM2S_ARVALID;
|
||||
assign M_AXI_MM2S_rready = axi_datamover_0_M_AXI_MM2S_RREADY;
|
||||
assign M_AXI_S2MM_awaddr[31:0] = axi_datamover_0_M_AXI_S2MM_AWADDR;
|
||||
assign M_AXI_S2MM_awburst[1:0] = axi_datamover_0_M_AXI_S2MM_AWBURST;
|
||||
assign M_AXI_S2MM_awcache[3:0] = axi_datamover_0_M_AXI_S2MM_AWCACHE;
|
||||
assign M_AXI_S2MM_awid[3:0] = axi_datamover_0_M_AXI_S2MM_AWID;
|
||||
assign M_AXI_S2MM_awlen[7:0] = axi_datamover_0_M_AXI_S2MM_AWLEN;
|
||||
assign M_AXI_S2MM_awprot[2:0] = axi_datamover_0_M_AXI_S2MM_AWPROT;
|
||||
assign M_AXI_S2MM_awsize[2:0] = axi_datamover_0_M_AXI_S2MM_AWSIZE;
|
||||
assign M_AXI_S2MM_awuser[3:0] = axi_datamover_0_M_AXI_S2MM_AWUSER;
|
||||
assign M_AXI_S2MM_awvalid = axi_datamover_0_M_AXI_S2MM_AWVALID;
|
||||
assign M_AXI_S2MM_bready = axi_datamover_0_M_AXI_S2MM_BREADY;
|
||||
assign M_AXI_S2MM_wdata[127:0] = axi_datamover_0_M_AXI_S2MM_WDATA;
|
||||
assign M_AXI_S2MM_wlast = axi_datamover_0_M_AXI_S2MM_WLAST;
|
||||
assign M_AXI_S2MM_wstrb[15:0] = axi_datamover_0_M_AXI_S2MM_WSTRB;
|
||||
assign M_AXI_S2MM_wvalid = axi_datamover_0_M_AXI_S2MM_WVALID;
|
||||
assign S_AXI_0_1_ARADDR = S_AXI_TXDESC_araddr[14:0];
|
||||
assign S_AXI_0_1_ARBURST = S_AXI_TXDESC_arburst[1:0];
|
||||
assign S_AXI_0_1_ARCACHE = S_AXI_TXDESC_arcache[3:0];
|
||||
assign S_AXI_0_1_ARLEN = S_AXI_TXDESC_arlen[7:0];
|
||||
assign S_AXI_0_1_ARLOCK = S_AXI_TXDESC_arlock;
|
||||
assign S_AXI_0_1_ARPROT = S_AXI_TXDESC_arprot[2:0];
|
||||
assign S_AXI_0_1_ARSIZE = S_AXI_TXDESC_arsize[2:0];
|
||||
assign S_AXI_0_1_ARVALID = S_AXI_TXDESC_arvalid;
|
||||
assign S_AXI_0_1_AWADDR = S_AXI_TXDESC_awaddr[14:0];
|
||||
assign S_AXI_0_1_AWBURST = S_AXI_TXDESC_awburst[1:0];
|
||||
assign S_AXI_0_1_AWCACHE = S_AXI_TXDESC_awcache[3:0];
|
||||
assign S_AXI_0_1_AWLEN = S_AXI_TXDESC_awlen[7:0];
|
||||
assign S_AXI_0_1_AWLOCK = S_AXI_TXDESC_awlock;
|
||||
assign S_AXI_0_1_AWPROT = S_AXI_TXDESC_awprot[2:0];
|
||||
assign S_AXI_0_1_AWSIZE = S_AXI_TXDESC_awsize[2:0];
|
||||
assign S_AXI_0_1_AWVALID = S_AXI_TXDESC_awvalid;
|
||||
assign S_AXI_0_1_BREADY = S_AXI_TXDESC_bready;
|
||||
assign S_AXI_0_1_RREADY = S_AXI_TXDESC_rready;
|
||||
assign S_AXI_0_1_WDATA = S_AXI_TXDESC_wdata[63:0];
|
||||
assign S_AXI_0_1_WLAST = S_AXI_TXDESC_wlast;
|
||||
assign S_AXI_0_1_WSTRB = S_AXI_TXDESC_wstrb[7:0];
|
||||
assign S_AXI_0_1_WVALID = S_AXI_TXDESC_wvalid;
|
||||
assign S_AXI_TXDESC_arready = S_AXI_0_1_ARREADY;
|
||||
assign S_AXI_TXDESC_awready = S_AXI_0_1_AWREADY;
|
||||
assign S_AXI_TXDESC_bresp[1:0] = S_AXI_0_1_BRESP;
|
||||
assign S_AXI_TXDESC_bvalid = S_AXI_0_1_BVALID;
|
||||
assign S_AXI_TXDESC_rdata[63:0] = S_AXI_0_1_RDATA;
|
||||
assign S_AXI_TXDESC_rlast = S_AXI_0_1_RLAST;
|
||||
assign S_AXI_TXDESC_rresp[1:0] = S_AXI_0_1_RRESP;
|
||||
assign S_AXI_TXDESC_rvalid = S_AXI_0_1_RVALID;
|
||||
assign S_AXI_TXDESC_wready = S_AXI_0_1_WREADY;
|
||||
assign aclk_0_1 = clk;
|
||||
assign aresetn_0_1 = aresetn;
|
||||
assign axi_datamover_0_M_AXI_MM2S_ARREADY = M_AXI_MM2S_arready;
|
||||
assign axi_datamover_0_M_AXI_MM2S_RDATA = M_AXI_MM2S_rdata[127:0];
|
||||
assign axi_datamover_0_M_AXI_MM2S_RLAST = M_AXI_MM2S_rlast;
|
||||
assign axi_datamover_0_M_AXI_MM2S_RRESP = M_AXI_MM2S_rresp[1:0];
|
||||
assign axi_datamover_0_M_AXI_MM2S_RVALID = M_AXI_MM2S_rvalid;
|
||||
assign axi_datamover_0_M_AXI_S2MM_AWREADY = M_AXI_S2MM_awready;
|
||||
assign axi_datamover_0_M_AXI_S2MM_BRESP = M_AXI_S2MM_bresp[1:0];
|
||||
assign axi_datamover_0_M_AXI_S2MM_BVALID = M_AXI_S2MM_bvalid;
|
||||
assign axi_datamover_0_M_AXI_S2MM_WREADY = M_AXI_S2MM_wready;
|
||||
assign s_axil_0_1_ARADDR = s_axil_rx_araddr[31:0];
|
||||
assign s_axil_0_1_ARPROT = s_axil_rx_arprot[2:0];
|
||||
assign s_axil_0_1_ARVALID = s_axil_rx_arvalid;
|
||||
assign s_axil_0_1_AWADDR = s_axil_rx_awaddr[31:0];
|
||||
assign s_axil_0_1_AWPROT = s_axil_rx_awprot[2:0];
|
||||
assign s_axil_0_1_AWVALID = s_axil_rx_awvalid;
|
||||
assign s_axil_0_1_BREADY = s_axil_rx_bready;
|
||||
assign s_axil_0_1_RREADY = s_axil_rx_rready;
|
||||
assign s_axil_0_1_WDATA = s_axil_rx_wdata[31:0];
|
||||
assign s_axil_0_1_WSTRB = s_axil_rx_wstrb[3:0];
|
||||
assign s_axil_0_1_WVALID = s_axil_rx_wvalid;
|
||||
assign s_axil_0_2_ARADDR = s_axil_tx_araddr[31:0];
|
||||
assign s_axil_0_2_ARPROT = s_axil_tx_arprot[2:0];
|
||||
assign s_axil_0_2_ARVALID = s_axil_tx_arvalid;
|
||||
assign s_axil_0_2_AWADDR = s_axil_tx_awaddr[31:0];
|
||||
assign s_axil_0_2_AWPROT = s_axil_tx_awprot[2:0];
|
||||
assign s_axil_0_2_AWVALID = s_axil_tx_awvalid;
|
||||
assign s_axil_0_2_BREADY = s_axil_tx_bready;
|
||||
assign s_axil_0_2_RREADY = s_axil_tx_rready;
|
||||
assign s_axil_0_2_WDATA = s_axil_tx_wdata[31:0];
|
||||
assign s_axil_0_2_WSTRB = s_axil_tx_wstrb[3:0];
|
||||
assign s_axil_0_2_WVALID = s_axil_tx_wvalid;
|
||||
assign s_axil_rx_arready = s_axil_0_1_ARREADY;
|
||||
assign s_axil_rx_awready = s_axil_0_1_AWREADY;
|
||||
assign s_axil_rx_bresp[1:0] = s_axil_0_1_BRESP;
|
||||
assign s_axil_rx_bvalid = s_axil_0_1_BVALID;
|
||||
assign s_axil_rx_rdata[31:0] = s_axil_0_1_RDATA;
|
||||
assign s_axil_rx_rresp[1:0] = s_axil_0_1_RRESP;
|
||||
assign s_axil_rx_rvalid = s_axil_0_1_RVALID;
|
||||
assign s_axil_rx_wready = s_axil_0_1_WREADY;
|
||||
assign s_axil_tx_arready = s_axil_0_2_ARREADY;
|
||||
assign s_axil_tx_awready = s_axil_0_2_AWREADY;
|
||||
assign s_axil_tx_bresp[1:0] = s_axil_0_2_BRESP;
|
||||
assign s_axil_tx_bvalid = s_axil_0_2_BVALID;
|
||||
assign s_axil_tx_rdata[31:0] = s_axil_0_2_RDATA;
|
||||
assign s_axil_tx_rresp[1:0] = s_axil_0_2_RRESP;
|
||||
assign s_axil_tx_rvalid = s_axil_0_2_RVALID;
|
||||
assign s_axil_tx_wready = s_axil_0_2_WREADY;
|
||||
assign ssp_clk_0_1 = ssp_rx_clk;
|
||||
assign ssp_csn_0_1 = ssp_rx_csn;
|
||||
assign ssp_data_0_1 = ssp_rx_data;
|
||||
assign ssp_tx_clk = ssp_tx_0_ssp_clk;
|
||||
assign ssp_tx_csn = ssp_tx_0_ssp_csn;
|
||||
assign ssp_tx_data = ssp_tx_0_ssp_data;
|
||||
ssp_combo_axi_bram_ctrl_0_0 axi_bram_ctrl_0
|
||||
(.bram_addr_a(axi_bram_ctrl_0_bram_addr_a),
|
||||
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
|
||||
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
|
||||
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
|
||||
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
|
||||
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
|
||||
.s_axi_aclk(aclk_0_1),
|
||||
.s_axi_araddr(S_AXI_0_1_ARADDR),
|
||||
.s_axi_arburst(S_AXI_0_1_ARBURST),
|
||||
.s_axi_arcache(S_AXI_0_1_ARCACHE),
|
||||
.s_axi_aresetn(aresetn_0_1),
|
||||
.s_axi_arlen(S_AXI_0_1_ARLEN),
|
||||
.s_axi_arlock(S_AXI_0_1_ARLOCK),
|
||||
.s_axi_arprot(S_AXI_0_1_ARPROT),
|
||||
.s_axi_arready(S_AXI_0_1_ARREADY),
|
||||
.s_axi_arsize(S_AXI_0_1_ARSIZE),
|
||||
.s_axi_arvalid(S_AXI_0_1_ARVALID),
|
||||
.s_axi_awaddr(S_AXI_0_1_AWADDR),
|
||||
.s_axi_awburst(S_AXI_0_1_AWBURST),
|
||||
.s_axi_awcache(S_AXI_0_1_AWCACHE),
|
||||
.s_axi_awlen(S_AXI_0_1_AWLEN),
|
||||
.s_axi_awlock(S_AXI_0_1_AWLOCK),
|
||||
.s_axi_awprot(S_AXI_0_1_AWPROT),
|
||||
.s_axi_awready(S_AXI_0_1_AWREADY),
|
||||
.s_axi_awsize(S_AXI_0_1_AWSIZE),
|
||||
.s_axi_awvalid(S_AXI_0_1_AWVALID),
|
||||
.s_axi_bready(S_AXI_0_1_BREADY),
|
||||
.s_axi_bresp(S_AXI_0_1_BRESP),
|
||||
.s_axi_bvalid(S_AXI_0_1_BVALID),
|
||||
.s_axi_rdata(S_AXI_0_1_RDATA),
|
||||
.s_axi_rlast(S_AXI_0_1_RLAST),
|
||||
.s_axi_rready(S_AXI_0_1_RREADY),
|
||||
.s_axi_rresp(S_AXI_0_1_RRESP),
|
||||
.s_axi_rvalid(S_AXI_0_1_RVALID),
|
||||
.s_axi_wdata(S_AXI_0_1_WDATA),
|
||||
.s_axi_wlast(S_AXI_0_1_WLAST),
|
||||
.s_axi_wready(S_AXI_0_1_WREADY),
|
||||
.s_axi_wstrb(S_AXI_0_1_WSTRB),
|
||||
.s_axi_wvalid(S_AXI_0_1_WVALID));
|
||||
ssp_combo_axi_datamover_0_0 axi_datamover_0
|
||||
(.m_axi_mm2s_aclk(aclk_0_1),
|
||||
.m_axi_mm2s_araddr(axi_datamover_0_M_AXI_MM2S_ARADDR),
|
||||
.m_axi_mm2s_arburst(axi_datamover_0_M_AXI_MM2S_ARBURST),
|
||||
.m_axi_mm2s_arcache(axi_datamover_0_M_AXI_MM2S_ARCACHE),
|
||||
.m_axi_mm2s_aresetn(aresetn_0_1),
|
||||
.m_axi_mm2s_arid(axi_datamover_0_M_AXI_MM2S_ARID),
|
||||
.m_axi_mm2s_arlen(axi_datamover_0_M_AXI_MM2S_ARLEN),
|
||||
.m_axi_mm2s_arprot(axi_datamover_0_M_AXI_MM2S_ARPROT),
|
||||
.m_axi_mm2s_arready(axi_datamover_0_M_AXI_MM2S_ARREADY),
|
||||
.m_axi_mm2s_arsize(axi_datamover_0_M_AXI_MM2S_ARSIZE),
|
||||
.m_axi_mm2s_aruser(axi_datamover_0_M_AXI_MM2S_ARUSER),
|
||||
.m_axi_mm2s_arvalid(axi_datamover_0_M_AXI_MM2S_ARVALID),
|
||||
.m_axi_mm2s_rdata(axi_datamover_0_M_AXI_MM2S_RDATA),
|
||||
.m_axi_mm2s_rlast(axi_datamover_0_M_AXI_MM2S_RLAST),
|
||||
.m_axi_mm2s_rready(axi_datamover_0_M_AXI_MM2S_RREADY),
|
||||
.m_axi_mm2s_rresp(axi_datamover_0_M_AXI_MM2S_RRESP),
|
||||
.m_axi_mm2s_rvalid(axi_datamover_0_M_AXI_MM2S_RVALID),
|
||||
.m_axi_s2mm_aclk(aclk_0_1),
|
||||
.m_axi_s2mm_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.m_axi_s2mm_awaddr(axi_datamover_0_M_AXI_S2MM_AWADDR),
|
||||
.m_axi_s2mm_awburst(axi_datamover_0_M_AXI_S2MM_AWBURST),
|
||||
.m_axi_s2mm_awcache(axi_datamover_0_M_AXI_S2MM_AWCACHE),
|
||||
.m_axi_s2mm_awid(axi_datamover_0_M_AXI_S2MM_AWID),
|
||||
.m_axi_s2mm_awlen(axi_datamover_0_M_AXI_S2MM_AWLEN),
|
||||
.m_axi_s2mm_awprot(axi_datamover_0_M_AXI_S2MM_AWPROT),
|
||||
.m_axi_s2mm_awready(axi_datamover_0_M_AXI_S2MM_AWREADY),
|
||||
.m_axi_s2mm_awsize(axi_datamover_0_M_AXI_S2MM_AWSIZE),
|
||||
.m_axi_s2mm_awuser(axi_datamover_0_M_AXI_S2MM_AWUSER),
|
||||
.m_axi_s2mm_awvalid(axi_datamover_0_M_AXI_S2MM_AWVALID),
|
||||
.m_axi_s2mm_bready(axi_datamover_0_M_AXI_S2MM_BREADY),
|
||||
.m_axi_s2mm_bresp(axi_datamover_0_M_AXI_S2MM_BRESP),
|
||||
.m_axi_s2mm_bvalid(axi_datamover_0_M_AXI_S2MM_BVALID),
|
||||
.m_axi_s2mm_wdata(axi_datamover_0_M_AXI_S2MM_WDATA),
|
||||
.m_axi_s2mm_wlast(axi_datamover_0_M_AXI_S2MM_WLAST),
|
||||
.m_axi_s2mm_wready(axi_datamover_0_M_AXI_S2MM_WREADY),
|
||||
.m_axi_s2mm_wstrb(axi_datamover_0_M_AXI_S2MM_WSTRB),
|
||||
.m_axi_s2mm_wvalid(axi_datamover_0_M_AXI_S2MM_WVALID),
|
||||
.m_axis_mm2s_cmdsts_aclk(aclk_0_1),
|
||||
.m_axis_mm2s_cmdsts_aresetn(aresetn_0_1),
|
||||
.m_axis_mm2s_sts_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
|
||||
.m_axis_mm2s_sts_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
|
||||
.m_axis_mm2s_sts_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
|
||||
.m_axis_mm2s_sts_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
|
||||
.m_axis_mm2s_sts_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID),
|
||||
.m_axis_mm2s_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
|
||||
.m_axis_mm2s_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
|
||||
.m_axis_mm2s_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
|
||||
.m_axis_mm2s_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
|
||||
.m_axis_mm2s_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID),
|
||||
.m_axis_s2mm_cmdsts_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.m_axis_s2mm_cmdsts_awclk(aclk_0_1),
|
||||
.m_axis_s2mm_sts_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
|
||||
.m_axis_s2mm_sts_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
|
||||
.m_axis_s2mm_sts_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
|
||||
.m_axis_s2mm_sts_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
|
||||
.m_axis_s2mm_sts_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID),
|
||||
.mm2s_err(axi_datamover_0_mm2s_err),
|
||||
.s2mm_err(axi_datamover_0_s2mm_err),
|
||||
.s_axis_mm2s_cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
|
||||
.s_axis_mm2s_cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
|
||||
.s_axis_mm2s_cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
|
||||
.s_axis_s2mm_cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
|
||||
.s_axis_s2mm_cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
|
||||
.s_axis_s2mm_cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
|
||||
.s_axis_s2mm_tdata(axis_data_fifo_0_M_AXIS_TDATA),
|
||||
.s_axis_s2mm_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
|
||||
.s_axis_s2mm_tlast(axis_data_fifo_0_M_AXIS_TLAST),
|
||||
.s_axis_s2mm_tready(axis_data_fifo_0_M_AXIS_TREADY),
|
||||
.s_axis_s2mm_tvalid(axis_data_fifo_0_M_AXIS_TVALID));
|
||||
ssp_combo_axil_reg_if_0_0 axil_reg_if_0
|
||||
(.aclk(aclk_0_1),
|
||||
.aresetn(aresetn_0_1),
|
||||
.reg_rd_ack(regfile_0_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_0_reg_rd_addr),
|
||||
.reg_rd_data(regfile_0_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_0_reg_rd_en),
|
||||
.reg_rd_wait(regfile_0_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_0_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_0_reg_wr_addr),
|
||||
.reg_wr_data(axil_reg_if_0_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_0_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_0_reg_wr_wait),
|
||||
.s_axil_araddr(s_axil_0_1_ARADDR),
|
||||
.s_axil_arprot(s_axil_0_1_ARPROT),
|
||||
.s_axil_arready(s_axil_0_1_ARREADY),
|
||||
.s_axil_arvalid(s_axil_0_1_ARVALID),
|
||||
.s_axil_awaddr(s_axil_0_1_AWADDR),
|
||||
.s_axil_awprot(s_axil_0_1_AWPROT),
|
||||
.s_axil_awready(s_axil_0_1_AWREADY),
|
||||
.s_axil_awvalid(s_axil_0_1_AWVALID),
|
||||
.s_axil_bready(s_axil_0_1_BREADY),
|
||||
.s_axil_bresp(s_axil_0_1_BRESP),
|
||||
.s_axil_bvalid(s_axil_0_1_BVALID),
|
||||
.s_axil_rdata(s_axil_0_1_RDATA),
|
||||
.s_axil_rready(s_axil_0_1_RREADY),
|
||||
.s_axil_rresp(s_axil_0_1_RRESP),
|
||||
.s_axil_rvalid(s_axil_0_1_RVALID),
|
||||
.s_axil_wdata(s_axil_0_1_WDATA),
|
||||
.s_axil_wready(s_axil_0_1_WREADY),
|
||||
.s_axil_wstrb(s_axil_0_1_WSTRB),
|
||||
.s_axil_wvalid(s_axil_0_1_WVALID));
|
||||
ssp_combo_axil_reg_if_1_0 axil_reg_if_1
|
||||
(.aclk(aclk_0_1),
|
||||
.aresetn(aresetn_0_1),
|
||||
.reg_rd_ack(regfile_1_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_1_reg_rd_addr),
|
||||
.reg_rd_data(regfile_1_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_1_reg_rd_en),
|
||||
.reg_rd_wait(regfile_1_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_1_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_1_reg_wr_addr),
|
||||
.reg_wr_data(axil_reg_if_1_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_1_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_1_reg_wr_wait),
|
||||
.s_axil_araddr(s_axil_0_2_ARADDR),
|
||||
.s_axil_arprot(s_axil_0_2_ARPROT),
|
||||
.s_axil_arready(s_axil_0_2_ARREADY),
|
||||
.s_axil_arvalid(s_axil_0_2_ARVALID),
|
||||
.s_axil_awaddr(s_axil_0_2_AWADDR),
|
||||
.s_axil_awprot(s_axil_0_2_AWPROT),
|
||||
.s_axil_awready(s_axil_0_2_AWREADY),
|
||||
.s_axil_awvalid(s_axil_0_2_AWVALID),
|
||||
.s_axil_bready(s_axil_0_2_BREADY),
|
||||
.s_axil_bresp(s_axil_0_2_BRESP),
|
||||
.s_axil_bvalid(s_axil_0_2_BVALID),
|
||||
.s_axil_rdata(s_axil_0_2_RDATA),
|
||||
.s_axil_rready(s_axil_0_2_RREADY),
|
||||
.s_axil_rresp(s_axil_0_2_RRESP),
|
||||
.s_axil_rvalid(s_axil_0_2_RVALID),
|
||||
.s_axil_wdata(s_axil_0_2_WDATA),
|
||||
.s_axil_wready(s_axil_0_2_WREADY),
|
||||
.s_axil_wstrb(s_axil_0_2_WSTRB),
|
||||
.s_axil_wvalid(s_axil_0_2_WVALID));
|
||||
ssp_combo_axis_data_fifo_0_0 axis_data_fifo_0
|
||||
(.m_axis_tdata(axis_data_fifo_0_M_AXIS_TDATA),
|
||||
.m_axis_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
|
||||
.m_axis_tlast(axis_data_fifo_0_M_AXIS_TLAST),
|
||||
.m_axis_tready(axis_data_fifo_0_M_AXIS_TREADY),
|
||||
.m_axis_tvalid(axis_data_fifo_0_M_AXIS_TVALID),
|
||||
.s_axis_aclk(aclk_0_1),
|
||||
.s_axis_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.s_axis_tdata(stream_rx_ctrl_0_egress_TDATA),
|
||||
.s_axis_tkeep(stream_rx_ctrl_0_egress_TKEEP),
|
||||
.s_axis_tlast(stream_rx_ctrl_0_egress_TLAST),
|
||||
.s_axis_tready(stream_rx_ctrl_0_egress_TREADY),
|
||||
.s_axis_tstrb(stream_rx_ctrl_0_egress_TSTRB),
|
||||
.s_axis_tvalid(stream_rx_ctrl_0_egress_TVALID));
|
||||
ssp_combo_axis_data_fifo_1_0 axis_data_fifo_1
|
||||
(.m_axis_tdata(axis_data_fifo_1_M_AXIS_TDATA),
|
||||
.m_axis_tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
|
||||
.m_axis_tlast(axis_data_fifo_1_M_AXIS_TLAST),
|
||||
.m_axis_tready(axis_data_fifo_1_M_AXIS_TREADY),
|
||||
.m_axis_tvalid(axis_data_fifo_1_M_AXIS_TVALID),
|
||||
.s_axis_aclk(aclk_0_1),
|
||||
.s_axis_aresetn(aresetn_0_1),
|
||||
.s_axis_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
|
||||
.s_axis_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
|
||||
.s_axis_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
|
||||
.s_axis_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
|
||||
.s_axis_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID));
|
||||
ssp_combo_blk_mem_gen_0_0 blk_mem_gen_0
|
||||
(.addra(xlslice_0_Dout),
|
||||
.addrb(stream_tx_ctrl_0_desc_if_ADDR),
|
||||
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
|
||||
.clkb(stream_tx_ctrl_0_desc_if_CLK),
|
||||
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
|
||||
.dinb(stream_tx_ctrl_0_desc_if_DIN),
|
||||
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
|
||||
.doutb(stream_tx_ctrl_0_desc_if_DOUT),
|
||||
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
|
||||
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
|
||||
.web(stream_tx_ctrl_0_desc_if_WE));
|
||||
ssp_combo_regfile_0_0 regfile_0
|
||||
(.clk(aclk_0_1),
|
||||
.reg_0(regfile_0_reg_0),
|
||||
.reg_1(regfile_0_reg_1),
|
||||
.reg_2(regfile_0_reg_2),
|
||||
.reg_3(regfile_0_reg_3),
|
||||
.reg_4(regfile_0_reg_4),
|
||||
.reg_5(regfile_0_reg_5),
|
||||
.reg_6(regfile_0_reg_6),
|
||||
.reg_rd_ack(regfile_0_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_0_reg_rd_addr[7:0]),
|
||||
.reg_rd_data(regfile_0_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_0_reg_rd_en),
|
||||
.reg_rd_wait(regfile_0_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_0_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_0_reg_wr_addr[7:0]),
|
||||
.reg_wr_data(axil_reg_if_0_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_0_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_0_reg_wr_wait),
|
||||
.resetn(aresetn_0_1),
|
||||
.status_0(stream_rx_ctrl_0_status_00),
|
||||
.status_1(stream_rx_ctrl_0_status_01),
|
||||
.status_10(ssp_rx_0_status_02),
|
||||
.status_11(ssp_rx_0_status_03),
|
||||
.status_12(ssp_rx_0_status_04),
|
||||
.status_13(ssp_rx_0_status_05),
|
||||
.status_14(ssp_rx_0_status_06),
|
||||
.status_15(ssp_rx_0_status_07),
|
||||
.status_2(stream_rx_ctrl_0_status_02),
|
||||
.status_3(stream_rx_ctrl_0_status_03),
|
||||
.status_4(stream_rx_ctrl_0_status_04),
|
||||
.status_5(stream_rx_ctrl_0_status_05),
|
||||
.status_6(stream_rx_ctrl_0_status_06),
|
||||
.status_7(stream_rx_ctrl_0_status_07),
|
||||
.status_8(ssp_rx_0_status_00),
|
||||
.status_9(ssp_rx_0_status_01));
|
||||
ssp_combo_regfile_1_0 regfile_1
|
||||
(.clk(aclk_0_1),
|
||||
.reg_0(regfile_1_reg_0),
|
||||
.reg_1(regfile_1_reg_1),
|
||||
.reg_2(regfile_1_reg_2),
|
||||
.reg_3(regfile_1_reg_3),
|
||||
.reg_4(regfile_1_reg_4),
|
||||
.reg_rd_ack(regfile_1_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_1_reg_rd_addr[7:0]),
|
||||
.reg_rd_data(regfile_1_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_1_reg_rd_en),
|
||||
.reg_rd_wait(regfile_1_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_1_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_1_reg_wr_addr[7:0]),
|
||||
.reg_wr_data(axil_reg_if_1_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_1_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_1_reg_wr_wait),
|
||||
.resetn(aresetn_0_1),
|
||||
.status_0(stream_tx_ctrl_0_status_00),
|
||||
.status_1(stream_tx_ctrl_0_status_01),
|
||||
.status_10(ssp_tx_0_status_02),
|
||||
.status_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_2(stream_tx_ctrl_0_status_02),
|
||||
.status_3(stream_tx_ctrl_0_status_03),
|
||||
.status_4(stream_tx_ctrl_0_status_04),
|
||||
.status_5(ssp_tx_0_tx_data_count),
|
||||
.status_6(ssp_tx_0_tx_last_count),
|
||||
.status_7(ssp_tx_0_status),
|
||||
.status_8(ssp_tx_0_status_00),
|
||||
.status_9(ssp_tx_0_status_01));
|
||||
ssp_combo_ssp_rx_0_0 ssp_rx_0
|
||||
(.aresetn(aresetn_0_1),
|
||||
.clk(aclk_0_1),
|
||||
.config_00(regfile_0_reg_4),
|
||||
.config_01(regfile_0_reg_5),
|
||||
.config_02(regfile_0_reg_6),
|
||||
.enable(stream_rx_ctrl_0_enable),
|
||||
.ssp_clk(ssp_clk_0_1),
|
||||
.ssp_csn(ssp_csn_0_1),
|
||||
.ssp_data(ssp_data_0_1),
|
||||
.status_00(ssp_rx_0_status_00),
|
||||
.status_01(ssp_rx_0_status_01),
|
||||
.status_02(ssp_rx_0_status_02),
|
||||
.status_03(ssp_rx_0_status_03),
|
||||
.status_04(ssp_rx_0_status_04),
|
||||
.status_05(ssp_rx_0_status_05),
|
||||
.status_06(ssp_rx_0_status_06),
|
||||
.status_07(ssp_rx_0_status_07),
|
||||
.tdata(ssp_rx_0_interface_axis_TDATA),
|
||||
.tkeep(ssp_rx_0_interface_axis_TKEEP),
|
||||
.tlast(ssp_rx_0_interface_axis_TLAST),
|
||||
.tready(ssp_rx_0_interface_axis_TREADY),
|
||||
.tstrb(ssp_rx_0_interface_axis_TSTRB),
|
||||
.tvalid(ssp_rx_0_interface_axis_TVALID));
|
||||
ssp_combo_ssp_tx_0_0 ssp_tx_0
|
||||
(.aresetn(aresetn_0_1),
|
||||
.clk(aclk_0_1),
|
||||
.config_00(regfile_1_reg_4),
|
||||
.ssp_clk(ssp_tx_0_ssp_clk),
|
||||
.ssp_csn(ssp_tx_0_ssp_csn),
|
||||
.ssp_data(ssp_tx_0_ssp_data),
|
||||
.status_00(ssp_tx_0_status_00),
|
||||
.status_01(ssp_tx_0_status_01),
|
||||
.status_02(ssp_tx_0_status_02),
|
||||
.tdata(axis_data_fifo_1_M_AXIS_TDATA),
|
||||
.tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
|
||||
.tlast(axis_data_fifo_1_M_AXIS_TLAST),
|
||||
.tready(axis_data_fifo_1_M_AXIS_TREADY),
|
||||
.tstrb(1'b1),
|
||||
.tvalid(axis_data_fifo_1_M_AXIS_TVALID));
|
||||
ssp_combo_stream_rx_ctrl_0_0 stream_rx_ctrl_0
|
||||
(.clk(aclk_0_1),
|
||||
.cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
|
||||
.cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
|
||||
.cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
|
||||
.config_00(regfile_0_reg_0),
|
||||
.config_01(regfile_0_reg_1),
|
||||
.config_02(regfile_0_reg_2),
|
||||
.config_03(regfile_0_reg_3),
|
||||
.egress_tdata(stream_rx_ctrl_0_egress_TDATA),
|
||||
.egress_tkeep(stream_rx_ctrl_0_egress_TKEEP),
|
||||
.egress_tlast(stream_rx_ctrl_0_egress_TLAST),
|
||||
.egress_tready(stream_rx_ctrl_0_egress_TREADY),
|
||||
.egress_tstrb(stream_rx_ctrl_0_egress_TSTRB),
|
||||
.egress_tvalid(stream_rx_ctrl_0_egress_TVALID),
|
||||
.enable(stream_rx_ctrl_0_enable),
|
||||
.ingress_tdata(ssp_rx_0_interface_axis_TDATA),
|
||||
.ingress_tkeep(ssp_rx_0_interface_axis_TKEEP),
|
||||
.ingress_tlast(ssp_rx_0_interface_axis_TLAST),
|
||||
.ingress_tready(ssp_rx_0_interface_axis_TREADY),
|
||||
.ingress_tstrb(ssp_rx_0_interface_axis_TSTRB),
|
||||
.ingress_tvalid(ssp_rx_0_interface_axis_TVALID),
|
||||
.rst_n(aresetn_0_1),
|
||||
.s2mm_err(axi_datamover_0_s2mm_err),
|
||||
.s2mm_resetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.status_00(stream_rx_ctrl_0_status_00),
|
||||
.status_01(stream_rx_ctrl_0_status_01),
|
||||
.status_02(stream_rx_ctrl_0_status_02),
|
||||
.status_03(stream_rx_ctrl_0_status_03),
|
||||
.status_04(stream_rx_ctrl_0_status_04),
|
||||
.status_05(stream_rx_ctrl_0_status_05),
|
||||
.status_06(stream_rx_ctrl_0_status_06),
|
||||
.status_07(stream_rx_ctrl_0_status_07),
|
||||
.status_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
|
||||
.status_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
|
||||
.status_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
|
||||
.status_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
|
||||
.status_tstrb({1'b1,1'b1,1'b1,1'b1}),
|
||||
.status_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID));
|
||||
ssp_combo_stream_tx_ctrl_0_0 stream_tx_ctrl_0
|
||||
(.clk(aclk_0_1),
|
||||
.cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
|
||||
.cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
|
||||
.cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
|
||||
.config_00(regfile_1_reg_0),
|
||||
.config_01(regfile_1_reg_1),
|
||||
.config_02(regfile_1_reg_2),
|
||||
.config_03(regfile_1_reg_3),
|
||||
.desc_addr(stream_tx_ctrl_0_desc_if_ADDR),
|
||||
.desc_clk(stream_tx_ctrl_0_desc_if_CLK),
|
||||
.desc_rdata(stream_tx_ctrl_0_desc_if_DOUT),
|
||||
.desc_wdata(stream_tx_ctrl_0_desc_if_DIN),
|
||||
.desc_we(stream_tx_ctrl_0_desc_if_WE),
|
||||
.mm2s_err(axi_datamover_0_mm2s_err),
|
||||
.rst_n(aresetn_0_1),
|
||||
.status_00(stream_tx_ctrl_0_status_00),
|
||||
.status_01(stream_tx_ctrl_0_status_01),
|
||||
.status_02(stream_tx_ctrl_0_status_02),
|
||||
.status_03(stream_tx_ctrl_0_status_03),
|
||||
.status_04(stream_tx_ctrl_0_status_04),
|
||||
.status_05(ssp_tx_0_tx_data_count),
|
||||
.status_06(ssp_tx_0_tx_last_count),
|
||||
.status_07(ssp_tx_0_status),
|
||||
.status_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
|
||||
.status_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
|
||||
.status_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
|
||||
.status_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
|
||||
.status_tstrb(1'b1),
|
||||
.status_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID));
|
||||
ssp_combo_xlslice_0_0 xlslice_0
|
||||
(.Din(axi_bram_ctrl_0_bram_addr_a[13:0]),
|
||||
.Dout(xlslice_0_Dout));
|
||||
endmodule
|
||||
333
ssp_combo/src/design_1_wrapper.v
Normal file
333
ssp_combo/src/design_1_wrapper.v
Normal file
@@ -0,0 +1,333 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
//Date : Mon Feb 2 14:59:42 2026
|
||||
//Host : le-ThinkStation running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_wrapper.bd
|
||||
//Design : design_1_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_wrapper
|
||||
(M_AXI_MM2S_araddr,
|
||||
M_AXI_MM2S_arburst,
|
||||
M_AXI_MM2S_arcache,
|
||||
M_AXI_MM2S_arid,
|
||||
M_AXI_MM2S_arlen,
|
||||
M_AXI_MM2S_arprot,
|
||||
M_AXI_MM2S_arready,
|
||||
M_AXI_MM2S_arsize,
|
||||
M_AXI_MM2S_aruser,
|
||||
M_AXI_MM2S_arvalid,
|
||||
M_AXI_MM2S_rdata,
|
||||
M_AXI_MM2S_rlast,
|
||||
M_AXI_MM2S_rready,
|
||||
M_AXI_MM2S_rresp,
|
||||
M_AXI_MM2S_rvalid,
|
||||
M_AXI_S2MM_awaddr,
|
||||
M_AXI_S2MM_awburst,
|
||||
M_AXI_S2MM_awcache,
|
||||
M_AXI_S2MM_awid,
|
||||
M_AXI_S2MM_awlen,
|
||||
M_AXI_S2MM_awprot,
|
||||
M_AXI_S2MM_awready,
|
||||
M_AXI_S2MM_awsize,
|
||||
M_AXI_S2MM_awuser,
|
||||
M_AXI_S2MM_awvalid,
|
||||
M_AXI_S2MM_bready,
|
||||
M_AXI_S2MM_bresp,
|
||||
M_AXI_S2MM_bvalid,
|
||||
M_AXI_S2MM_wdata,
|
||||
M_AXI_S2MM_wlast,
|
||||
M_AXI_S2MM_wready,
|
||||
M_AXI_S2MM_wstrb,
|
||||
M_AXI_S2MM_wvalid,
|
||||
aresetn,
|
||||
clk,
|
||||
s_axil_rx_araddr,
|
||||
s_axil_rx_arprot,
|
||||
s_axil_rx_arready,
|
||||
s_axil_rx_arvalid,
|
||||
s_axil_rx_awaddr,
|
||||
s_axil_rx_awprot,
|
||||
s_axil_rx_awready,
|
||||
s_axil_rx_awvalid,
|
||||
s_axil_rx_bready,
|
||||
s_axil_rx_bresp,
|
||||
s_axil_rx_bvalid,
|
||||
s_axil_rx_rdata,
|
||||
s_axil_rx_rready,
|
||||
s_axil_rx_rresp,
|
||||
s_axil_rx_rvalid,
|
||||
s_axil_rx_wdata,
|
||||
s_axil_rx_wready,
|
||||
s_axil_rx_wstrb,
|
||||
s_axil_rx_wvalid,
|
||||
s_axil_tx_araddr,
|
||||
s_axil_tx_arprot,
|
||||
s_axil_tx_arready,
|
||||
s_axil_tx_arvalid,
|
||||
s_axil_tx_awaddr,
|
||||
s_axil_tx_awprot,
|
||||
s_axil_tx_awready,
|
||||
s_axil_tx_awvalid,
|
||||
s_axil_tx_bready,
|
||||
s_axil_tx_bresp,
|
||||
s_axil_tx_bvalid,
|
||||
s_axil_tx_rdata,
|
||||
s_axil_tx_rready,
|
||||
s_axil_tx_rresp,
|
||||
s_axil_tx_rvalid,
|
||||
s_axil_tx_wdata,
|
||||
s_axil_tx_wready,
|
||||
s_axil_tx_wstrb,
|
||||
s_axil_tx_wvalid,
|
||||
ssp_rx_clk,
|
||||
ssp_rx_csn,
|
||||
ssp_rx_data,
|
||||
ssp_tx_clk,
|
||||
ssp_tx_csn,
|
||||
ssp_tx_data);
|
||||
output [31:0]M_AXI_MM2S_araddr;
|
||||
output [1:0]M_AXI_MM2S_arburst;
|
||||
output [3:0]M_AXI_MM2S_arcache;
|
||||
output [3:0]M_AXI_MM2S_arid;
|
||||
output [7:0]M_AXI_MM2S_arlen;
|
||||
output [2:0]M_AXI_MM2S_arprot;
|
||||
input M_AXI_MM2S_arready;
|
||||
output [2:0]M_AXI_MM2S_arsize;
|
||||
output [3:0]M_AXI_MM2S_aruser;
|
||||
output M_AXI_MM2S_arvalid;
|
||||
input [127:0]M_AXI_MM2S_rdata;
|
||||
input M_AXI_MM2S_rlast;
|
||||
output M_AXI_MM2S_rready;
|
||||
input [1:0]M_AXI_MM2S_rresp;
|
||||
input M_AXI_MM2S_rvalid;
|
||||
output [31:0]M_AXI_S2MM_awaddr;
|
||||
output [1:0]M_AXI_S2MM_awburst;
|
||||
output [3:0]M_AXI_S2MM_awcache;
|
||||
output [3:0]M_AXI_S2MM_awid;
|
||||
output [7:0]M_AXI_S2MM_awlen;
|
||||
output [2:0]M_AXI_S2MM_awprot;
|
||||
input M_AXI_S2MM_awready;
|
||||
output [2:0]M_AXI_S2MM_awsize;
|
||||
output [3:0]M_AXI_S2MM_awuser;
|
||||
output M_AXI_S2MM_awvalid;
|
||||
output M_AXI_S2MM_bready;
|
||||
input [1:0]M_AXI_S2MM_bresp;
|
||||
input M_AXI_S2MM_bvalid;
|
||||
output [127:0]M_AXI_S2MM_wdata;
|
||||
output M_AXI_S2MM_wlast;
|
||||
input M_AXI_S2MM_wready;
|
||||
output [15:0]M_AXI_S2MM_wstrb;
|
||||
output M_AXI_S2MM_wvalid;
|
||||
input aresetn;
|
||||
input clk;
|
||||
input [31:0]s_axil_rx_araddr;
|
||||
input [2:0]s_axil_rx_arprot;
|
||||
output s_axil_rx_arready;
|
||||
input s_axil_rx_arvalid;
|
||||
input [31:0]s_axil_rx_awaddr;
|
||||
input [2:0]s_axil_rx_awprot;
|
||||
output s_axil_rx_awready;
|
||||
input s_axil_rx_awvalid;
|
||||
input s_axil_rx_bready;
|
||||
output [1:0]s_axil_rx_bresp;
|
||||
output s_axil_rx_bvalid;
|
||||
output [31:0]s_axil_rx_rdata;
|
||||
input s_axil_rx_rready;
|
||||
output [1:0]s_axil_rx_rresp;
|
||||
output s_axil_rx_rvalid;
|
||||
input [31:0]s_axil_rx_wdata;
|
||||
output s_axil_rx_wready;
|
||||
input [3:0]s_axil_rx_wstrb;
|
||||
input s_axil_rx_wvalid;
|
||||
input [31:0]s_axil_tx_araddr;
|
||||
input [2:0]s_axil_tx_arprot;
|
||||
output s_axil_tx_arready;
|
||||
input s_axil_tx_arvalid;
|
||||
input [31:0]s_axil_tx_awaddr;
|
||||
input [2:0]s_axil_tx_awprot;
|
||||
output s_axil_tx_awready;
|
||||
input s_axil_tx_awvalid;
|
||||
input s_axil_tx_bready;
|
||||
output [1:0]s_axil_tx_bresp;
|
||||
output s_axil_tx_bvalid;
|
||||
output [31:0]s_axil_tx_rdata;
|
||||
input s_axil_tx_rready;
|
||||
output [1:0]s_axil_tx_rresp;
|
||||
output s_axil_tx_rvalid;
|
||||
input [31:0]s_axil_tx_wdata;
|
||||
output s_axil_tx_wready;
|
||||
input [3:0]s_axil_tx_wstrb;
|
||||
input s_axil_tx_wvalid;
|
||||
input ssp_rx_clk;
|
||||
input ssp_rx_csn;
|
||||
input ssp_rx_data;
|
||||
output ssp_tx_clk;
|
||||
output ssp_tx_csn;
|
||||
output ssp_tx_data;
|
||||
|
||||
wire [31:0]M_AXI_MM2S_araddr;
|
||||
wire [1:0]M_AXI_MM2S_arburst;
|
||||
wire [3:0]M_AXI_MM2S_arcache;
|
||||
wire [3:0]M_AXI_MM2S_arid;
|
||||
wire [7:0]M_AXI_MM2S_arlen;
|
||||
wire [2:0]M_AXI_MM2S_arprot;
|
||||
wire M_AXI_MM2S_arready;
|
||||
wire [2:0]M_AXI_MM2S_arsize;
|
||||
wire [3:0]M_AXI_MM2S_aruser;
|
||||
wire M_AXI_MM2S_arvalid;
|
||||
wire [127:0]M_AXI_MM2S_rdata;
|
||||
wire M_AXI_MM2S_rlast;
|
||||
wire M_AXI_MM2S_rready;
|
||||
wire [1:0]M_AXI_MM2S_rresp;
|
||||
wire M_AXI_MM2S_rvalid;
|
||||
wire [31:0]M_AXI_S2MM_awaddr;
|
||||
wire [1:0]M_AXI_S2MM_awburst;
|
||||
wire [3:0]M_AXI_S2MM_awcache;
|
||||
wire [3:0]M_AXI_S2MM_awid;
|
||||
wire [7:0]M_AXI_S2MM_awlen;
|
||||
wire [2:0]M_AXI_S2MM_awprot;
|
||||
wire M_AXI_S2MM_awready;
|
||||
wire [2:0]M_AXI_S2MM_awsize;
|
||||
wire [3:0]M_AXI_S2MM_awuser;
|
||||
wire M_AXI_S2MM_awvalid;
|
||||
wire M_AXI_S2MM_bready;
|
||||
wire [1:0]M_AXI_S2MM_bresp;
|
||||
wire M_AXI_S2MM_bvalid;
|
||||
wire [127:0]M_AXI_S2MM_wdata;
|
||||
wire M_AXI_S2MM_wlast;
|
||||
wire M_AXI_S2MM_wready;
|
||||
wire [15:0]M_AXI_S2MM_wstrb;
|
||||
wire M_AXI_S2MM_wvalid;
|
||||
wire aresetn;
|
||||
wire clk;
|
||||
wire [31:0]s_axil_rx_araddr;
|
||||
wire [2:0]s_axil_rx_arprot;
|
||||
wire s_axil_rx_arready;
|
||||
wire s_axil_rx_arvalid;
|
||||
wire [31:0]s_axil_rx_awaddr;
|
||||
wire [2:0]s_axil_rx_awprot;
|
||||
wire s_axil_rx_awready;
|
||||
wire s_axil_rx_awvalid;
|
||||
wire s_axil_rx_bready;
|
||||
wire [1:0]s_axil_rx_bresp;
|
||||
wire s_axil_rx_bvalid;
|
||||
wire [31:0]s_axil_rx_rdata;
|
||||
wire s_axil_rx_rready;
|
||||
wire [1:0]s_axil_rx_rresp;
|
||||
wire s_axil_rx_rvalid;
|
||||
wire [31:0]s_axil_rx_wdata;
|
||||
wire s_axil_rx_wready;
|
||||
wire [3:0]s_axil_rx_wstrb;
|
||||
wire s_axil_rx_wvalid;
|
||||
wire [31:0]s_axil_tx_araddr;
|
||||
wire [2:0]s_axil_tx_arprot;
|
||||
wire s_axil_tx_arready;
|
||||
wire s_axil_tx_arvalid;
|
||||
wire [31:0]s_axil_tx_awaddr;
|
||||
wire [2:0]s_axil_tx_awprot;
|
||||
wire s_axil_tx_awready;
|
||||
wire s_axil_tx_awvalid;
|
||||
wire s_axil_tx_bready;
|
||||
wire [1:0]s_axil_tx_bresp;
|
||||
wire s_axil_tx_bvalid;
|
||||
wire [31:0]s_axil_tx_rdata;
|
||||
wire s_axil_tx_rready;
|
||||
wire [1:0]s_axil_tx_rresp;
|
||||
wire s_axil_tx_rvalid;
|
||||
wire [31:0]s_axil_tx_wdata;
|
||||
wire s_axil_tx_wready;
|
||||
wire [3:0]s_axil_tx_wstrb;
|
||||
wire s_axil_tx_wvalid;
|
||||
wire ssp_rx_clk;
|
||||
wire ssp_rx_csn;
|
||||
wire ssp_rx_data;
|
||||
wire ssp_tx_clk;
|
||||
wire ssp_tx_csn;
|
||||
wire ssp_tx_data;
|
||||
|
||||
design_1 design_1_i
|
||||
(.M_AXI_MM2S_araddr(M_AXI_MM2S_araddr),
|
||||
.M_AXI_MM2S_arburst(M_AXI_MM2S_arburst),
|
||||
.M_AXI_MM2S_arcache(M_AXI_MM2S_arcache),
|
||||
.M_AXI_MM2S_arid(M_AXI_MM2S_arid),
|
||||
.M_AXI_MM2S_arlen(M_AXI_MM2S_arlen),
|
||||
.M_AXI_MM2S_arprot(M_AXI_MM2S_arprot),
|
||||
.M_AXI_MM2S_arready(M_AXI_MM2S_arready),
|
||||
.M_AXI_MM2S_arsize(M_AXI_MM2S_arsize),
|
||||
.M_AXI_MM2S_aruser(M_AXI_MM2S_aruser),
|
||||
.M_AXI_MM2S_arvalid(M_AXI_MM2S_arvalid),
|
||||
.M_AXI_MM2S_rdata(M_AXI_MM2S_rdata),
|
||||
.M_AXI_MM2S_rlast(M_AXI_MM2S_rlast),
|
||||
.M_AXI_MM2S_rready(M_AXI_MM2S_rready),
|
||||
.M_AXI_MM2S_rresp(M_AXI_MM2S_rresp),
|
||||
.M_AXI_MM2S_rvalid(M_AXI_MM2S_rvalid),
|
||||
.M_AXI_S2MM_awaddr(M_AXI_S2MM_awaddr),
|
||||
.M_AXI_S2MM_awburst(M_AXI_S2MM_awburst),
|
||||
.M_AXI_S2MM_awcache(M_AXI_S2MM_awcache),
|
||||
.M_AXI_S2MM_awid(M_AXI_S2MM_awid),
|
||||
.M_AXI_S2MM_awlen(M_AXI_S2MM_awlen),
|
||||
.M_AXI_S2MM_awprot(M_AXI_S2MM_awprot),
|
||||
.M_AXI_S2MM_awready(M_AXI_S2MM_awready),
|
||||
.M_AXI_S2MM_awsize(M_AXI_S2MM_awsize),
|
||||
.M_AXI_S2MM_awuser(M_AXI_S2MM_awuser),
|
||||
.M_AXI_S2MM_awvalid(M_AXI_S2MM_awvalid),
|
||||
.M_AXI_S2MM_bready(M_AXI_S2MM_bready),
|
||||
.M_AXI_S2MM_bresp(M_AXI_S2MM_bresp),
|
||||
.M_AXI_S2MM_bvalid(M_AXI_S2MM_bvalid),
|
||||
.M_AXI_S2MM_wdata(M_AXI_S2MM_wdata),
|
||||
.M_AXI_S2MM_wlast(M_AXI_S2MM_wlast),
|
||||
.M_AXI_S2MM_wready(M_AXI_S2MM_wready),
|
||||
.M_AXI_S2MM_wstrb(M_AXI_S2MM_wstrb),
|
||||
.M_AXI_S2MM_wvalid(M_AXI_S2MM_wvalid),
|
||||
.aresetn(aresetn),
|
||||
.clk(clk),
|
||||
.s_axil_rx_araddr(s_axil_rx_araddr),
|
||||
.s_axil_rx_arprot(s_axil_rx_arprot),
|
||||
.s_axil_rx_arready(s_axil_rx_arready),
|
||||
.s_axil_rx_arvalid(s_axil_rx_arvalid),
|
||||
.s_axil_rx_awaddr(s_axil_rx_awaddr),
|
||||
.s_axil_rx_awprot(s_axil_rx_awprot),
|
||||
.s_axil_rx_awready(s_axil_rx_awready),
|
||||
.s_axil_rx_awvalid(s_axil_rx_awvalid),
|
||||
.s_axil_rx_bready(s_axil_rx_bready),
|
||||
.s_axil_rx_bresp(s_axil_rx_bresp),
|
||||
.s_axil_rx_bvalid(s_axil_rx_bvalid),
|
||||
.s_axil_rx_rdata(s_axil_rx_rdata),
|
||||
.s_axil_rx_rready(s_axil_rx_rready),
|
||||
.s_axil_rx_rresp(s_axil_rx_rresp),
|
||||
.s_axil_rx_rvalid(s_axil_rx_rvalid),
|
||||
.s_axil_rx_wdata(s_axil_rx_wdata),
|
||||
.s_axil_rx_wready(s_axil_rx_wready),
|
||||
.s_axil_rx_wstrb(s_axil_rx_wstrb),
|
||||
.s_axil_rx_wvalid(s_axil_rx_wvalid),
|
||||
.s_axil_tx_araddr(s_axil_tx_araddr),
|
||||
.s_axil_tx_arprot(s_axil_tx_arprot),
|
||||
.s_axil_tx_arready(s_axil_tx_arready),
|
||||
.s_axil_tx_arvalid(s_axil_tx_arvalid),
|
||||
.s_axil_tx_awaddr(s_axil_tx_awaddr),
|
||||
.s_axil_tx_awprot(s_axil_tx_awprot),
|
||||
.s_axil_tx_awready(s_axil_tx_awready),
|
||||
.s_axil_tx_awvalid(s_axil_tx_awvalid),
|
||||
.s_axil_tx_bready(s_axil_tx_bready),
|
||||
.s_axil_tx_bresp(s_axil_tx_bresp),
|
||||
.s_axil_tx_bvalid(s_axil_tx_bvalid),
|
||||
.s_axil_tx_rdata(s_axil_tx_rdata),
|
||||
.s_axil_tx_rready(s_axil_tx_rready),
|
||||
.s_axil_tx_rresp(s_axil_tx_rresp),
|
||||
.s_axil_tx_rvalid(s_axil_tx_rvalid),
|
||||
.s_axil_tx_wdata(s_axil_tx_wdata),
|
||||
.s_axil_tx_wready(s_axil_tx_wready),
|
||||
.s_axil_tx_wstrb(s_axil_tx_wstrb),
|
||||
.s_axil_tx_wvalid(s_axil_tx_wvalid),
|
||||
.ssp_rx_clk(ssp_rx_clk),
|
||||
.ssp_rx_csn(ssp_rx_csn),
|
||||
.ssp_rx_data(ssp_rx_data),
|
||||
.ssp_tx_clk(ssp_tx_clk),
|
||||
.ssp_tx_csn(ssp_tx_csn),
|
||||
.ssp_tx_data(ssp_tx_data));
|
||||
endmodule
|
||||
111
ssp_combo/src/ssp_card.xdc
Normal file
111
ssp_combo/src/ssp_card.xdc
Normal file
@@ -0,0 +1,111 @@
|
||||
##################PCIe reset define####################################
|
||||
set_property PACKAGE_PIN J20 [get_ports sys_rst_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]
|
||||
set_property PULLTYPE PULLUP [get_ports sys_rst_n]
|
||||
set_false_path -from [get_ports sys_rst_n]
|
||||
|
||||
###########################define PCIe clock############################
|
||||
set_property PACKAGE_PIN F10 [get_ports {pcie_ref_clk_p[0]}]
|
||||
set_property PACKAGE_PIN E10 [get_ports {pcie_ref_clk_n[0]}]
|
||||
create_clock -period 10.000 -name pcie_ref_clk_p [get_ports pcie_ref_clk_p]
|
||||
|
||||
set_property PACKAGE_PIN R4 [get_ports {clk_200m_clk_p}]
|
||||
set_property PACKAGE_PIN T4 [get_ports {clk_200m_clk_n}]
|
||||
set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_200m_clk_p}]
|
||||
set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_200m_clk_n}]
|
||||
create_clock -period 5.000 -name clk_200m_clk_p [get_ports clk_200m_clk_p]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN N15 [get_ports uart_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
|
||||
set_property PACKAGE_PIN P20 [get_ports uart_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
|
||||
|
||||
|
||||
#######################################################################
|
||||
# LVDS port
|
||||
set_property PACKAGE_PIN W16 [get_ports ssp_tx_clk_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_clk_0]
|
||||
set_property PACKAGE_PIN U15 [get_ports ssp_tx_csn_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_csn_0]
|
||||
set_property PACKAGE_PIN AA21 [get_ports ssp_tx_data_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_data_0]
|
||||
|
||||
set_property PACKAGE_PIN P16 [get_ports ssp_rx_clk_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_clk_0]
|
||||
set_property PACKAGE_PIN N17 [get_ports ssp_rx_csn_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_csn_0]
|
||||
set_property PACKAGE_PIN U17 [get_ports ssp_rx_data_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_data_0]
|
||||
|
||||
|
||||
#######################################################################
|
||||
# PCM port
|
||||
#set_property PACKAGE_PIN U20 [get_ports ssp_tx_clk_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_clk_0]
|
||||
#set_property PACKAGE_PIN P19 [get_ports ssp_tx_csn_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_csn_0]
|
||||
#set_property PACKAGE_PIN U16 [get_ports ssp_tx_data_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_tx_data_0]
|
||||
#
|
||||
#set_property PACKAGE_PIN V18 [get_ports ssp_rx_clk_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_clk_0]
|
||||
#set_property PACKAGE_PIN U17 [get_ports ssp_rx_csn_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_csn_0]
|
||||
#set_property PACKAGE_PIN N17 [get_ports ssp_rx_data_0]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ssp_rx_data_0]
|
||||
|
||||
|
||||
|
||||
########################################################################
|
||||
# [Vivado 12-1411] Cannot set LOC property of ports, design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i Instance design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i can not be placed in GTPE2_CHANNEL of site GTPE2_CHANNEL_X0Y5 because the bel is occupied by design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i. This could be caused by bel constraint conflict ["E:/workspace2/AX7203/ax7203_xdma_test/ax7203_xdma_test.srcs/constrs_1/new/ax7203_xdma_test.xdc":29]
|
||||
|
||||
########################################################################
|
||||
# PCIe Lane 0
|
||||
# PCIe Lane 1
|
||||
# PCIe Lane 2
|
||||
# PCIe Lane 3
|
||||
|
||||
# GTP Common Placement
|
||||
set_property LOC GTPE2_COMMON_X0Y1 [get_cells {design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtp_common.gtpe2_common_i}]
|
||||
|
||||
set_property LOC PCIE_X0Y0 [get_cells design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/pcie_top_i/pcie_7x_i/pcie_block_i]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
|
||||
set_property PACKAGE_PIN C11 [get_ports {pcie_rxn[0]}]
|
||||
set_property PACKAGE_PIN D11 [get_ports {pcie_rxp[0]}]
|
||||
set_property PACKAGE_PIN C5 [get_ports {pcie_txn[0]}]
|
||||
set_property PACKAGE_PIN D5 [get_ports {pcie_txp[0]}]
|
||||
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
|
||||
set_property PACKAGE_PIN A8 [get_ports {pcie_rxn[1]}]
|
||||
set_property PACKAGE_PIN B8 [get_ports {pcie_rxp[1]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {pcie_txn[1]}]
|
||||
set_property PACKAGE_PIN B4 [get_ports {pcie_txp[1]}]
|
||||
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells {design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {pcie_rxn[2]}]
|
||||
set_property PACKAGE_PIN B10 [get_ports {pcie_rxp[2]}]
|
||||
set_property PACKAGE_PIN A6 [get_ports {pcie_txn[2]}]
|
||||
set_property PACKAGE_PIN B6 [get_ports {pcie_txp[2]}]
|
||||
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells {design_1_i/xdma_0/inst/design_1_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
|
||||
set_property PACKAGE_PIN C9 [get_ports {pcie_rxn[3]}]
|
||||
set_property PACKAGE_PIN D9 [get_ports {pcie_rxp[3]}]
|
||||
set_property PACKAGE_PIN C7 [get_ports {pcie_txn[3]}]
|
||||
set_property PACKAGE_PIN D7 [get_ports {pcie_txp[3]}]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN D14 [get_ports user_lnk_up]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_lnk_up]
|
||||
|
||||
######################define flash loading speed#######################
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
|
||||
976
ssp_combo/src/ssp_combo.v
Normal file
976
ssp_combo/src/ssp_combo.v
Normal file
@@ -0,0 +1,976 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
//Date : Mon Feb 2 19:53:39 2026
|
||||
//Host : le-ThinkStation running 64-bit major release (build 9200)
|
||||
//Command : generate_target ssp_combo.bd
|
||||
//Design : ssp_combo
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ssp_combo,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ssp_combo,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "ssp_combo.hwdef" *)
|
||||
module ssp_combo
|
||||
(M_AXI_MM2S_araddr,
|
||||
M_AXI_MM2S_arburst,
|
||||
M_AXI_MM2S_arcache,
|
||||
M_AXI_MM2S_arid,
|
||||
M_AXI_MM2S_arlen,
|
||||
M_AXI_MM2S_arprot,
|
||||
M_AXI_MM2S_arready,
|
||||
M_AXI_MM2S_arsize,
|
||||
M_AXI_MM2S_aruser,
|
||||
M_AXI_MM2S_arvalid,
|
||||
M_AXI_MM2S_rdata,
|
||||
M_AXI_MM2S_rlast,
|
||||
M_AXI_MM2S_rready,
|
||||
M_AXI_MM2S_rresp,
|
||||
M_AXI_MM2S_rvalid,
|
||||
M_AXI_S2MM_awaddr,
|
||||
M_AXI_S2MM_awburst,
|
||||
M_AXI_S2MM_awcache,
|
||||
M_AXI_S2MM_awid,
|
||||
M_AXI_S2MM_awlen,
|
||||
M_AXI_S2MM_awprot,
|
||||
M_AXI_S2MM_awready,
|
||||
M_AXI_S2MM_awsize,
|
||||
M_AXI_S2MM_awuser,
|
||||
M_AXI_S2MM_awvalid,
|
||||
M_AXI_S2MM_bready,
|
||||
M_AXI_S2MM_bresp,
|
||||
M_AXI_S2MM_bvalid,
|
||||
M_AXI_S2MM_wdata,
|
||||
M_AXI_S2MM_wlast,
|
||||
M_AXI_S2MM_wready,
|
||||
M_AXI_S2MM_wstrb,
|
||||
M_AXI_S2MM_wvalid,
|
||||
S_AXI_TXDESC_araddr,
|
||||
S_AXI_TXDESC_arburst,
|
||||
S_AXI_TXDESC_arcache,
|
||||
S_AXI_TXDESC_arlen,
|
||||
S_AXI_TXDESC_arlock,
|
||||
S_AXI_TXDESC_arprot,
|
||||
S_AXI_TXDESC_arready,
|
||||
S_AXI_TXDESC_arsize,
|
||||
S_AXI_TXDESC_arvalid,
|
||||
S_AXI_TXDESC_awaddr,
|
||||
S_AXI_TXDESC_awburst,
|
||||
S_AXI_TXDESC_awcache,
|
||||
S_AXI_TXDESC_awlen,
|
||||
S_AXI_TXDESC_awlock,
|
||||
S_AXI_TXDESC_awprot,
|
||||
S_AXI_TXDESC_awready,
|
||||
S_AXI_TXDESC_awsize,
|
||||
S_AXI_TXDESC_awvalid,
|
||||
S_AXI_TXDESC_bready,
|
||||
S_AXI_TXDESC_bresp,
|
||||
S_AXI_TXDESC_bvalid,
|
||||
S_AXI_TXDESC_rdata,
|
||||
S_AXI_TXDESC_rlast,
|
||||
S_AXI_TXDESC_rready,
|
||||
S_AXI_TXDESC_rresp,
|
||||
S_AXI_TXDESC_rvalid,
|
||||
S_AXI_TXDESC_wdata,
|
||||
S_AXI_TXDESC_wlast,
|
||||
S_AXI_TXDESC_wready,
|
||||
S_AXI_TXDESC_wstrb,
|
||||
S_AXI_TXDESC_wvalid,
|
||||
aresetn,
|
||||
clk,
|
||||
s_axil_rx_araddr,
|
||||
s_axil_rx_arprot,
|
||||
s_axil_rx_arready,
|
||||
s_axil_rx_arvalid,
|
||||
s_axil_rx_awaddr,
|
||||
s_axil_rx_awprot,
|
||||
s_axil_rx_awready,
|
||||
s_axil_rx_awvalid,
|
||||
s_axil_rx_bready,
|
||||
s_axil_rx_bresp,
|
||||
s_axil_rx_bvalid,
|
||||
s_axil_rx_rdata,
|
||||
s_axil_rx_rready,
|
||||
s_axil_rx_rresp,
|
||||
s_axil_rx_rvalid,
|
||||
s_axil_rx_wdata,
|
||||
s_axil_rx_wready,
|
||||
s_axil_rx_wstrb,
|
||||
s_axil_rx_wvalid,
|
||||
s_axil_tx_araddr,
|
||||
s_axil_tx_arprot,
|
||||
s_axil_tx_arready,
|
||||
s_axil_tx_arvalid,
|
||||
s_axil_tx_awaddr,
|
||||
s_axil_tx_awprot,
|
||||
s_axil_tx_awready,
|
||||
s_axil_tx_awvalid,
|
||||
s_axil_tx_bready,
|
||||
s_axil_tx_bresp,
|
||||
s_axil_tx_bvalid,
|
||||
s_axil_tx_rdata,
|
||||
s_axil_tx_rready,
|
||||
s_axil_tx_rresp,
|
||||
s_axil_tx_rvalid,
|
||||
s_axil_tx_wdata,
|
||||
s_axil_tx_wready,
|
||||
s_axil_tx_wstrb,
|
||||
s_axil_tx_wvalid,
|
||||
ssp_rx_clk,
|
||||
ssp_rx_csn,
|
||||
ssp_rx_data,
|
||||
ssp_tx_clk,
|
||||
ssp_tx_csn,
|
||||
ssp_tx_data);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_MM2S, ADDR_WIDTH 32, ARUSER_WIDTH 4, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 0, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 0, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_MM2S_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST" *) output [1:0]M_AXI_MM2S_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE" *) output [3:0]M_AXI_MM2S_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID" *) output [3:0]M_AXI_MM2S_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]M_AXI_MM2S_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT" *) output [2:0]M_AXI_MM2S_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY" *) input M_AXI_MM2S_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]M_AXI_MM2S_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER" *) output [3:0]M_AXI_MM2S_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID" *) output M_AXI_MM2S_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA" *) input [127:0]M_AXI_MM2S_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST" *) input M_AXI_MM2S_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY" *) output M_AXI_MM2S_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP" *) input [1:0]M_AXI_MM2S_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID" *) input M_AXI_MM2S_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_S2MM, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 4, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 0, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE WRITE_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_S2MM_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST" *) output [1:0]M_AXI_S2MM_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE" *) output [3:0]M_AXI_S2MM_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID" *) output [3:0]M_AXI_S2MM_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN" *) output [7:0]M_AXI_S2MM_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT" *) output [2:0]M_AXI_S2MM_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY" *) input M_AXI_S2MM_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE" *) output [2:0]M_AXI_S2MM_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER" *) output [3:0]M_AXI_S2MM_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID" *) output M_AXI_S2MM_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY" *) output M_AXI_S2MM_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP" *) input [1:0]M_AXI_S2MM_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID" *) input M_AXI_S2MM_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA" *) output [127:0]M_AXI_S2MM_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST" *) output M_AXI_S2MM_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY" *) input M_AXI_S2MM_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB" *) output [15:0]M_AXI_S2MM_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID" *) output M_AXI_S2MM_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_TXDESC, ADDR_WIDTH 15, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 64, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [14:0]S_AXI_TXDESC_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARBURST" *) input [1:0]S_AXI_TXDESC_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARCACHE" *) input [3:0]S_AXI_TXDESC_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLEN" *) input [7:0]S_AXI_TXDESC_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLOCK" *) input S_AXI_TXDESC_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARPROT" *) input [2:0]S_AXI_TXDESC_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARREADY" *) output S_AXI_TXDESC_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARSIZE" *) input [2:0]S_AXI_TXDESC_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARVALID" *) input S_AXI_TXDESC_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWADDR" *) input [14:0]S_AXI_TXDESC_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWBURST" *) input [1:0]S_AXI_TXDESC_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWCACHE" *) input [3:0]S_AXI_TXDESC_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLEN" *) input [7:0]S_AXI_TXDESC_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLOCK" *) input S_AXI_TXDESC_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWPROT" *) input [2:0]S_AXI_TXDESC_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWREADY" *) output S_AXI_TXDESC_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWSIZE" *) input [2:0]S_AXI_TXDESC_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWVALID" *) input S_AXI_TXDESC_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BREADY" *) input S_AXI_TXDESC_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BRESP" *) output [1:0]S_AXI_TXDESC_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BVALID" *) output S_AXI_TXDESC_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RDATA" *) output [63:0]S_AXI_TXDESC_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RLAST" *) output S_AXI_TXDESC_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RREADY" *) input S_AXI_TXDESC_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RRESP" *) output [1:0]S_AXI_TXDESC_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RVALID" *) output S_AXI_TXDESC_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WDATA" *) input [63:0]S_AXI_TXDESC_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WLAST" *) input S_AXI_TXDESC_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WREADY" *) output S_AXI_TXDESC_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WSTRB" *) input [7:0]S_AXI_TXDESC_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WVALID" *) input S_AXI_TXDESC_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXI_S2MM:s_axil_rx:s_axil_tx:S_AXI_TXDESC, ASSOCIATED_RESET aresetn, CLK_DOMAIN ssp_combo_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_rx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_rx_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARPROT" *) input [2:0]s_axil_rx_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARREADY" *) output s_axil_rx_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARVALID" *) input s_axil_rx_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWADDR" *) input [31:0]s_axil_rx_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWPROT" *) input [2:0]s_axil_rx_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWREADY" *) output s_axil_rx_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWVALID" *) input s_axil_rx_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BREADY" *) input s_axil_rx_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BRESP" *) output [1:0]s_axil_rx_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BVALID" *) output s_axil_rx_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RDATA" *) output [31:0]s_axil_rx_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RREADY" *) input s_axil_rx_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RRESP" *) output [1:0]s_axil_rx_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RVALID" *) output s_axil_rx_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WDATA" *) input [31:0]s_axil_rx_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WREADY" *) output s_axil_rx_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WSTRB" *) input [3:0]s_axil_rx_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WVALID" *) input s_axil_rx_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_tx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_tx_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARPROT" *) input [2:0]s_axil_tx_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARREADY" *) output s_axil_tx_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARVALID" *) input s_axil_tx_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWADDR" *) input [31:0]s_axil_tx_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWPROT" *) input [2:0]s_axil_tx_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWREADY" *) output s_axil_tx_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWVALID" *) input s_axil_tx_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BREADY" *) input s_axil_tx_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BRESP" *) output [1:0]s_axil_tx_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BVALID" *) output s_axil_tx_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RDATA" *) output [31:0]s_axil_tx_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RREADY" *) input s_axil_tx_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RRESP" *) output [1:0]s_axil_tx_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RVALID" *) output s_axil_tx_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WDATA" *) input [31:0]s_axil_tx_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WREADY" *) output s_axil_tx_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WSTRB" *) input [3:0]s_axil_tx_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WVALID" *) input s_axil_tx_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_RX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_RX_CLK, CLK_DOMAIN ssp_combo_ssp_rx_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input ssp_rx_clk;
|
||||
input ssp_rx_csn;
|
||||
input ssp_rx_data;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_TX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_TX_CLK, CLK_DOMAIN ssp_combo_ssp_tx_0_0_ssp_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) output ssp_tx_clk;
|
||||
output ssp_tx_csn;
|
||||
output ssp_tx_data;
|
||||
|
||||
wire [14:0]S_AXI_0_1_ARADDR;
|
||||
wire [1:0]S_AXI_0_1_ARBURST;
|
||||
wire [3:0]S_AXI_0_1_ARCACHE;
|
||||
wire [7:0]S_AXI_0_1_ARLEN;
|
||||
wire S_AXI_0_1_ARLOCK;
|
||||
wire [2:0]S_AXI_0_1_ARPROT;
|
||||
wire S_AXI_0_1_ARREADY;
|
||||
wire [2:0]S_AXI_0_1_ARSIZE;
|
||||
wire S_AXI_0_1_ARVALID;
|
||||
wire [14:0]S_AXI_0_1_AWADDR;
|
||||
wire [1:0]S_AXI_0_1_AWBURST;
|
||||
wire [3:0]S_AXI_0_1_AWCACHE;
|
||||
wire [7:0]S_AXI_0_1_AWLEN;
|
||||
wire S_AXI_0_1_AWLOCK;
|
||||
wire [2:0]S_AXI_0_1_AWPROT;
|
||||
wire S_AXI_0_1_AWREADY;
|
||||
wire [2:0]S_AXI_0_1_AWSIZE;
|
||||
wire S_AXI_0_1_AWVALID;
|
||||
wire S_AXI_0_1_BREADY;
|
||||
wire [1:0]S_AXI_0_1_BRESP;
|
||||
wire S_AXI_0_1_BVALID;
|
||||
wire [63:0]S_AXI_0_1_RDATA;
|
||||
wire S_AXI_0_1_RLAST;
|
||||
wire S_AXI_0_1_RREADY;
|
||||
wire [1:0]S_AXI_0_1_RRESP;
|
||||
wire S_AXI_0_1_RVALID;
|
||||
wire [63:0]S_AXI_0_1_WDATA;
|
||||
wire S_AXI_0_1_WLAST;
|
||||
wire S_AXI_0_1_WREADY;
|
||||
wire [7:0]S_AXI_0_1_WSTRB;
|
||||
wire S_AXI_0_1_WVALID;
|
||||
wire aclk_0_1;
|
||||
wire aresetn_0_1;
|
||||
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
|
||||
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
|
||||
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
|
||||
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
|
||||
wire [7:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
|
||||
wire [14:0]axi_bram_ctrl_0_bram_addr_a;
|
||||
wire [7:0]axi_datamover_0_M_AXIS_MM2S_STS_TDATA;
|
||||
wire [0:0]axi_datamover_0_M_AXIS_MM2S_STS_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_STS_TVALID;
|
||||
wire [7:0]axi_datamover_0_M_AXIS_MM2S_TDATA;
|
||||
wire [0:0]axi_datamover_0_M_AXIS_MM2S_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_MM2S_TVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXIS_S2MM_STS_TDATA;
|
||||
wire [3:0]axi_datamover_0_M_AXIS_S2MM_STS_TKEEP;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TLAST;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TREADY;
|
||||
wire axi_datamover_0_M_AXIS_S2MM_STS_TVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXI_MM2S_ARADDR;
|
||||
wire [1:0]axi_datamover_0_M_AXI_MM2S_ARBURST;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARCACHE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARID;
|
||||
wire [7:0]axi_datamover_0_M_AXI_MM2S_ARLEN;
|
||||
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARPROT;
|
||||
wire axi_datamover_0_M_AXI_MM2S_ARREADY;
|
||||
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARSIZE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARUSER;
|
||||
wire axi_datamover_0_M_AXI_MM2S_ARVALID;
|
||||
wire [127:0]axi_datamover_0_M_AXI_MM2S_RDATA;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RLAST;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RREADY;
|
||||
wire [1:0]axi_datamover_0_M_AXI_MM2S_RRESP;
|
||||
wire axi_datamover_0_M_AXI_MM2S_RVALID;
|
||||
wire [31:0]axi_datamover_0_M_AXI_S2MM_AWADDR;
|
||||
wire [1:0]axi_datamover_0_M_AXI_S2MM_AWBURST;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWCACHE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWID;
|
||||
wire [7:0]axi_datamover_0_M_AXI_S2MM_AWLEN;
|
||||
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWPROT;
|
||||
wire axi_datamover_0_M_AXI_S2MM_AWREADY;
|
||||
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWSIZE;
|
||||
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWUSER;
|
||||
wire axi_datamover_0_M_AXI_S2MM_AWVALID;
|
||||
wire axi_datamover_0_M_AXI_S2MM_BREADY;
|
||||
wire [1:0]axi_datamover_0_M_AXI_S2MM_BRESP;
|
||||
wire axi_datamover_0_M_AXI_S2MM_BVALID;
|
||||
wire [127:0]axi_datamover_0_M_AXI_S2MM_WDATA;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WLAST;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WREADY;
|
||||
wire [15:0]axi_datamover_0_M_AXI_S2MM_WSTRB;
|
||||
wire axi_datamover_0_M_AXI_S2MM_WVALID;
|
||||
wire axi_datamover_0_mm2s_err;
|
||||
wire axi_datamover_0_s2mm_err;
|
||||
wire [31:0]axil_reg_if_0_reg_rd_addr;
|
||||
wire axil_reg_if_0_reg_rd_en;
|
||||
wire [31:0]axil_reg_if_0_reg_wr_addr;
|
||||
wire [31:0]axil_reg_if_0_reg_wr_data;
|
||||
wire axil_reg_if_0_reg_wr_en;
|
||||
wire [3:0]axil_reg_if_0_reg_wr_strb;
|
||||
wire [31:0]axil_reg_if_1_reg_rd_addr;
|
||||
wire axil_reg_if_1_reg_rd_en;
|
||||
wire [31:0]axil_reg_if_1_reg_wr_addr;
|
||||
wire [31:0]axil_reg_if_1_reg_wr_data;
|
||||
wire axil_reg_if_1_reg_wr_en;
|
||||
wire [3:0]axil_reg_if_1_reg_wr_strb;
|
||||
wire [7:0]axis_data_fifo_0_M_AXIS_TDATA;
|
||||
wire [0:0]axis_data_fifo_0_M_AXIS_TKEEP;
|
||||
wire axis_data_fifo_0_M_AXIS_TLAST;
|
||||
wire axis_data_fifo_0_M_AXIS_TREADY;
|
||||
wire axis_data_fifo_0_M_AXIS_TVALID;
|
||||
wire [7:0]axis_data_fifo_1_M_AXIS_TDATA;
|
||||
wire [0:0]axis_data_fifo_1_M_AXIS_TKEEP;
|
||||
wire axis_data_fifo_1_M_AXIS_TLAST;
|
||||
wire axis_data_fifo_1_M_AXIS_TREADY;
|
||||
wire axis_data_fifo_1_M_AXIS_TVALID;
|
||||
wire [31:0]regfile_0_reg_0;
|
||||
wire [31:0]regfile_0_reg_1;
|
||||
wire [31:0]regfile_0_reg_2;
|
||||
wire [31:0]regfile_0_reg_3;
|
||||
wire [31:0]regfile_0_reg_4;
|
||||
wire [31:0]regfile_0_reg_5;
|
||||
wire [31:0]regfile_0_reg_6;
|
||||
wire regfile_0_reg_rd_ack;
|
||||
wire [31:0]regfile_0_reg_rd_data;
|
||||
wire regfile_0_reg_rd_wait;
|
||||
wire regfile_0_reg_wr_ack;
|
||||
wire regfile_0_reg_wr_wait;
|
||||
wire [31:0]regfile_1_reg_0;
|
||||
wire [31:0]regfile_1_reg_1;
|
||||
wire [31:0]regfile_1_reg_2;
|
||||
wire [31:0]regfile_1_reg_3;
|
||||
wire [31:0]regfile_1_reg_4;
|
||||
wire regfile_1_reg_rd_ack;
|
||||
wire [31:0]regfile_1_reg_rd_data;
|
||||
wire regfile_1_reg_rd_wait;
|
||||
wire regfile_1_reg_wr_ack;
|
||||
wire regfile_1_reg_wr_wait;
|
||||
wire [31:0]s_axil_0_1_ARADDR;
|
||||
wire [2:0]s_axil_0_1_ARPROT;
|
||||
wire s_axil_0_1_ARREADY;
|
||||
wire s_axil_0_1_ARVALID;
|
||||
wire [31:0]s_axil_0_1_AWADDR;
|
||||
wire [2:0]s_axil_0_1_AWPROT;
|
||||
wire s_axil_0_1_AWREADY;
|
||||
wire s_axil_0_1_AWVALID;
|
||||
wire s_axil_0_1_BREADY;
|
||||
wire [1:0]s_axil_0_1_BRESP;
|
||||
wire s_axil_0_1_BVALID;
|
||||
wire [31:0]s_axil_0_1_RDATA;
|
||||
wire s_axil_0_1_RREADY;
|
||||
wire [1:0]s_axil_0_1_RRESP;
|
||||
wire s_axil_0_1_RVALID;
|
||||
wire [31:0]s_axil_0_1_WDATA;
|
||||
wire s_axil_0_1_WREADY;
|
||||
wire [3:0]s_axil_0_1_WSTRB;
|
||||
wire s_axil_0_1_WVALID;
|
||||
wire [31:0]s_axil_0_2_ARADDR;
|
||||
wire [2:0]s_axil_0_2_ARPROT;
|
||||
wire s_axil_0_2_ARREADY;
|
||||
wire s_axil_0_2_ARVALID;
|
||||
wire [31:0]s_axil_0_2_AWADDR;
|
||||
wire [2:0]s_axil_0_2_AWPROT;
|
||||
wire s_axil_0_2_AWREADY;
|
||||
wire s_axil_0_2_AWVALID;
|
||||
wire s_axil_0_2_BREADY;
|
||||
wire [1:0]s_axil_0_2_BRESP;
|
||||
wire s_axil_0_2_BVALID;
|
||||
wire [31:0]s_axil_0_2_RDATA;
|
||||
wire s_axil_0_2_RREADY;
|
||||
wire [1:0]s_axil_0_2_RRESP;
|
||||
wire s_axil_0_2_RVALID;
|
||||
wire [31:0]s_axil_0_2_WDATA;
|
||||
wire s_axil_0_2_WREADY;
|
||||
wire [3:0]s_axil_0_2_WSTRB;
|
||||
wire s_axil_0_2_WVALID;
|
||||
wire ssp_clk_0_1;
|
||||
wire ssp_csn_0_1;
|
||||
wire ssp_data_0_1;
|
||||
wire [7:0]ssp_rx_0_interface_axis_TDATA;
|
||||
wire ssp_rx_0_interface_axis_TKEEP;
|
||||
wire ssp_rx_0_interface_axis_TLAST;
|
||||
wire ssp_rx_0_interface_axis_TREADY;
|
||||
wire ssp_rx_0_interface_axis_TSTRB;
|
||||
wire ssp_rx_0_interface_axis_TVALID;
|
||||
wire [31:0]ssp_rx_0_status_00;
|
||||
wire [31:0]ssp_rx_0_status_01;
|
||||
wire [31:0]ssp_rx_0_status_02;
|
||||
wire [31:0]ssp_rx_0_status_03;
|
||||
wire [31:0]ssp_rx_0_status_04;
|
||||
wire [31:0]ssp_rx_0_status_05;
|
||||
wire [31:0]ssp_rx_0_status_06;
|
||||
wire [31:0]ssp_rx_0_status_07;
|
||||
wire ssp_tx_0_ssp_clk;
|
||||
wire ssp_tx_0_ssp_csn;
|
||||
wire ssp_tx_0_ssp_data;
|
||||
wire [31:0]ssp_tx_0_status;
|
||||
wire [31:0]ssp_tx_0_status_00;
|
||||
wire [31:0]ssp_tx_0_status_01;
|
||||
wire [31:0]ssp_tx_0_status_02;
|
||||
wire [31:0]ssp_tx_0_tx_data_count;
|
||||
wire [31:0]ssp_tx_0_tx_last_count;
|
||||
wire [71:0]stream_rx_ctrl_0_cmd_TDATA;
|
||||
wire stream_rx_ctrl_0_cmd_TREADY;
|
||||
wire stream_rx_ctrl_0_cmd_TVALID;
|
||||
wire [7:0]stream_rx_ctrl_0_egress_TDATA;
|
||||
wire [0:0]stream_rx_ctrl_0_egress_TKEEP;
|
||||
wire stream_rx_ctrl_0_egress_TLAST;
|
||||
wire stream_rx_ctrl_0_egress_TREADY;
|
||||
wire [0:0]stream_rx_ctrl_0_egress_TSTRB;
|
||||
wire stream_rx_ctrl_0_egress_TVALID;
|
||||
wire stream_rx_ctrl_0_enable;
|
||||
wire stream_rx_ctrl_0_s2mm_resetn;
|
||||
wire [31:0]stream_rx_ctrl_0_status_00;
|
||||
wire [31:0]stream_rx_ctrl_0_status_01;
|
||||
wire [31:0]stream_rx_ctrl_0_status_02;
|
||||
wire [31:0]stream_rx_ctrl_0_status_03;
|
||||
wire [31:0]stream_rx_ctrl_0_status_04;
|
||||
wire [31:0]stream_rx_ctrl_0_status_05;
|
||||
wire [31:0]stream_rx_ctrl_0_status_06;
|
||||
wire [31:0]stream_rx_ctrl_0_status_07;
|
||||
wire [71:0]stream_tx_ctrl_0_cmd_TDATA;
|
||||
wire stream_tx_ctrl_0_cmd_TREADY;
|
||||
wire stream_tx_ctrl_0_cmd_TVALID;
|
||||
wire [10:0]stream_tx_ctrl_0_desc_if_ADDR;
|
||||
wire stream_tx_ctrl_0_desc_if_CLK;
|
||||
wire [63:0]stream_tx_ctrl_0_desc_if_DIN;
|
||||
wire [63:0]stream_tx_ctrl_0_desc_if_DOUT;
|
||||
wire [7:0]stream_tx_ctrl_0_desc_if_WE;
|
||||
wire [31:0]stream_tx_ctrl_0_status_00;
|
||||
wire [31:0]stream_tx_ctrl_0_status_01;
|
||||
wire [31:0]stream_tx_ctrl_0_status_02;
|
||||
wire [31:0]stream_tx_ctrl_0_status_03;
|
||||
wire [31:0]stream_tx_ctrl_0_status_04;
|
||||
wire [10:0]xlslice_0_Dout;
|
||||
|
||||
assign M_AXI_MM2S_araddr[31:0] = axi_datamover_0_M_AXI_MM2S_ARADDR;
|
||||
assign M_AXI_MM2S_arburst[1:0] = axi_datamover_0_M_AXI_MM2S_ARBURST;
|
||||
assign M_AXI_MM2S_arcache[3:0] = axi_datamover_0_M_AXI_MM2S_ARCACHE;
|
||||
assign M_AXI_MM2S_arid[3:0] = axi_datamover_0_M_AXI_MM2S_ARID;
|
||||
assign M_AXI_MM2S_arlen[7:0] = axi_datamover_0_M_AXI_MM2S_ARLEN;
|
||||
assign M_AXI_MM2S_arprot[2:0] = axi_datamover_0_M_AXI_MM2S_ARPROT;
|
||||
assign M_AXI_MM2S_arsize[2:0] = axi_datamover_0_M_AXI_MM2S_ARSIZE;
|
||||
assign M_AXI_MM2S_aruser[3:0] = axi_datamover_0_M_AXI_MM2S_ARUSER;
|
||||
assign M_AXI_MM2S_arvalid = axi_datamover_0_M_AXI_MM2S_ARVALID;
|
||||
assign M_AXI_MM2S_rready = axi_datamover_0_M_AXI_MM2S_RREADY;
|
||||
assign M_AXI_S2MM_awaddr[31:0] = axi_datamover_0_M_AXI_S2MM_AWADDR;
|
||||
assign M_AXI_S2MM_awburst[1:0] = axi_datamover_0_M_AXI_S2MM_AWBURST;
|
||||
assign M_AXI_S2MM_awcache[3:0] = axi_datamover_0_M_AXI_S2MM_AWCACHE;
|
||||
assign M_AXI_S2MM_awid[3:0] = axi_datamover_0_M_AXI_S2MM_AWID;
|
||||
assign M_AXI_S2MM_awlen[7:0] = axi_datamover_0_M_AXI_S2MM_AWLEN;
|
||||
assign M_AXI_S2MM_awprot[2:0] = axi_datamover_0_M_AXI_S2MM_AWPROT;
|
||||
assign M_AXI_S2MM_awsize[2:0] = axi_datamover_0_M_AXI_S2MM_AWSIZE;
|
||||
assign M_AXI_S2MM_awuser[3:0] = axi_datamover_0_M_AXI_S2MM_AWUSER;
|
||||
assign M_AXI_S2MM_awvalid = axi_datamover_0_M_AXI_S2MM_AWVALID;
|
||||
assign M_AXI_S2MM_bready = axi_datamover_0_M_AXI_S2MM_BREADY;
|
||||
assign M_AXI_S2MM_wdata[127:0] = axi_datamover_0_M_AXI_S2MM_WDATA;
|
||||
assign M_AXI_S2MM_wlast = axi_datamover_0_M_AXI_S2MM_WLAST;
|
||||
assign M_AXI_S2MM_wstrb[15:0] = axi_datamover_0_M_AXI_S2MM_WSTRB;
|
||||
assign M_AXI_S2MM_wvalid = axi_datamover_0_M_AXI_S2MM_WVALID;
|
||||
assign S_AXI_0_1_ARADDR = S_AXI_TXDESC_araddr[14:0];
|
||||
assign S_AXI_0_1_ARBURST = S_AXI_TXDESC_arburst[1:0];
|
||||
assign S_AXI_0_1_ARCACHE = S_AXI_TXDESC_arcache[3:0];
|
||||
assign S_AXI_0_1_ARLEN = S_AXI_TXDESC_arlen[7:0];
|
||||
assign S_AXI_0_1_ARLOCK = S_AXI_TXDESC_arlock;
|
||||
assign S_AXI_0_1_ARPROT = S_AXI_TXDESC_arprot[2:0];
|
||||
assign S_AXI_0_1_ARSIZE = S_AXI_TXDESC_arsize[2:0];
|
||||
assign S_AXI_0_1_ARVALID = S_AXI_TXDESC_arvalid;
|
||||
assign S_AXI_0_1_AWADDR = S_AXI_TXDESC_awaddr[14:0];
|
||||
assign S_AXI_0_1_AWBURST = S_AXI_TXDESC_awburst[1:0];
|
||||
assign S_AXI_0_1_AWCACHE = S_AXI_TXDESC_awcache[3:0];
|
||||
assign S_AXI_0_1_AWLEN = S_AXI_TXDESC_awlen[7:0];
|
||||
assign S_AXI_0_1_AWLOCK = S_AXI_TXDESC_awlock;
|
||||
assign S_AXI_0_1_AWPROT = S_AXI_TXDESC_awprot[2:0];
|
||||
assign S_AXI_0_1_AWSIZE = S_AXI_TXDESC_awsize[2:0];
|
||||
assign S_AXI_0_1_AWVALID = S_AXI_TXDESC_awvalid;
|
||||
assign S_AXI_0_1_BREADY = S_AXI_TXDESC_bready;
|
||||
assign S_AXI_0_1_RREADY = S_AXI_TXDESC_rready;
|
||||
assign S_AXI_0_1_WDATA = S_AXI_TXDESC_wdata[63:0];
|
||||
assign S_AXI_0_1_WLAST = S_AXI_TXDESC_wlast;
|
||||
assign S_AXI_0_1_WSTRB = S_AXI_TXDESC_wstrb[7:0];
|
||||
assign S_AXI_0_1_WVALID = S_AXI_TXDESC_wvalid;
|
||||
assign S_AXI_TXDESC_arready = S_AXI_0_1_ARREADY;
|
||||
assign S_AXI_TXDESC_awready = S_AXI_0_1_AWREADY;
|
||||
assign S_AXI_TXDESC_bresp[1:0] = S_AXI_0_1_BRESP;
|
||||
assign S_AXI_TXDESC_bvalid = S_AXI_0_1_BVALID;
|
||||
assign S_AXI_TXDESC_rdata[63:0] = S_AXI_0_1_RDATA;
|
||||
assign S_AXI_TXDESC_rlast = S_AXI_0_1_RLAST;
|
||||
assign S_AXI_TXDESC_rresp[1:0] = S_AXI_0_1_RRESP;
|
||||
assign S_AXI_TXDESC_rvalid = S_AXI_0_1_RVALID;
|
||||
assign S_AXI_TXDESC_wready = S_AXI_0_1_WREADY;
|
||||
assign aclk_0_1 = clk;
|
||||
assign aresetn_0_1 = aresetn;
|
||||
assign axi_datamover_0_M_AXI_MM2S_ARREADY = M_AXI_MM2S_arready;
|
||||
assign axi_datamover_0_M_AXI_MM2S_RDATA = M_AXI_MM2S_rdata[127:0];
|
||||
assign axi_datamover_0_M_AXI_MM2S_RLAST = M_AXI_MM2S_rlast;
|
||||
assign axi_datamover_0_M_AXI_MM2S_RRESP = M_AXI_MM2S_rresp[1:0];
|
||||
assign axi_datamover_0_M_AXI_MM2S_RVALID = M_AXI_MM2S_rvalid;
|
||||
assign axi_datamover_0_M_AXI_S2MM_AWREADY = M_AXI_S2MM_awready;
|
||||
assign axi_datamover_0_M_AXI_S2MM_BRESP = M_AXI_S2MM_bresp[1:0];
|
||||
assign axi_datamover_0_M_AXI_S2MM_BVALID = M_AXI_S2MM_bvalid;
|
||||
assign axi_datamover_0_M_AXI_S2MM_WREADY = M_AXI_S2MM_wready;
|
||||
assign s_axil_0_1_ARADDR = s_axil_rx_araddr[31:0];
|
||||
assign s_axil_0_1_ARPROT = s_axil_rx_arprot[2:0];
|
||||
assign s_axil_0_1_ARVALID = s_axil_rx_arvalid;
|
||||
assign s_axil_0_1_AWADDR = s_axil_rx_awaddr[31:0];
|
||||
assign s_axil_0_1_AWPROT = s_axil_rx_awprot[2:0];
|
||||
assign s_axil_0_1_AWVALID = s_axil_rx_awvalid;
|
||||
assign s_axil_0_1_BREADY = s_axil_rx_bready;
|
||||
assign s_axil_0_1_RREADY = s_axil_rx_rready;
|
||||
assign s_axil_0_1_WDATA = s_axil_rx_wdata[31:0];
|
||||
assign s_axil_0_1_WSTRB = s_axil_rx_wstrb[3:0];
|
||||
assign s_axil_0_1_WVALID = s_axil_rx_wvalid;
|
||||
assign s_axil_0_2_ARADDR = s_axil_tx_araddr[31:0];
|
||||
assign s_axil_0_2_ARPROT = s_axil_tx_arprot[2:0];
|
||||
assign s_axil_0_2_ARVALID = s_axil_tx_arvalid;
|
||||
assign s_axil_0_2_AWADDR = s_axil_tx_awaddr[31:0];
|
||||
assign s_axil_0_2_AWPROT = s_axil_tx_awprot[2:0];
|
||||
assign s_axil_0_2_AWVALID = s_axil_tx_awvalid;
|
||||
assign s_axil_0_2_BREADY = s_axil_tx_bready;
|
||||
assign s_axil_0_2_RREADY = s_axil_tx_rready;
|
||||
assign s_axil_0_2_WDATA = s_axil_tx_wdata[31:0];
|
||||
assign s_axil_0_2_WSTRB = s_axil_tx_wstrb[3:0];
|
||||
assign s_axil_0_2_WVALID = s_axil_tx_wvalid;
|
||||
assign s_axil_rx_arready = s_axil_0_1_ARREADY;
|
||||
assign s_axil_rx_awready = s_axil_0_1_AWREADY;
|
||||
assign s_axil_rx_bresp[1:0] = s_axil_0_1_BRESP;
|
||||
assign s_axil_rx_bvalid = s_axil_0_1_BVALID;
|
||||
assign s_axil_rx_rdata[31:0] = s_axil_0_1_RDATA;
|
||||
assign s_axil_rx_rresp[1:0] = s_axil_0_1_RRESP;
|
||||
assign s_axil_rx_rvalid = s_axil_0_1_RVALID;
|
||||
assign s_axil_rx_wready = s_axil_0_1_WREADY;
|
||||
assign s_axil_tx_arready = s_axil_0_2_ARREADY;
|
||||
assign s_axil_tx_awready = s_axil_0_2_AWREADY;
|
||||
assign s_axil_tx_bresp[1:0] = s_axil_0_2_BRESP;
|
||||
assign s_axil_tx_bvalid = s_axil_0_2_BVALID;
|
||||
assign s_axil_tx_rdata[31:0] = s_axil_0_2_RDATA;
|
||||
assign s_axil_tx_rresp[1:0] = s_axil_0_2_RRESP;
|
||||
assign s_axil_tx_rvalid = s_axil_0_2_RVALID;
|
||||
assign s_axil_tx_wready = s_axil_0_2_WREADY;
|
||||
assign ssp_clk_0_1 = ssp_rx_clk;
|
||||
assign ssp_csn_0_1 = ssp_rx_csn;
|
||||
assign ssp_data_0_1 = ssp_rx_data;
|
||||
assign ssp_tx_clk = ssp_tx_0_ssp_clk;
|
||||
assign ssp_tx_csn = ssp_tx_0_ssp_csn;
|
||||
assign ssp_tx_data = ssp_tx_0_ssp_data;
|
||||
ssp_combo_axi_bram_ctrl_0_0 axi_bram_ctrl_0
|
||||
(.bram_addr_a(axi_bram_ctrl_0_bram_addr_a),
|
||||
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
|
||||
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
|
||||
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
|
||||
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
|
||||
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
|
||||
.s_axi_aclk(aclk_0_1),
|
||||
.s_axi_araddr(S_AXI_0_1_ARADDR),
|
||||
.s_axi_arburst(S_AXI_0_1_ARBURST),
|
||||
.s_axi_arcache(S_AXI_0_1_ARCACHE),
|
||||
.s_axi_aresetn(aresetn_0_1),
|
||||
.s_axi_arlen(S_AXI_0_1_ARLEN),
|
||||
.s_axi_arlock(S_AXI_0_1_ARLOCK),
|
||||
.s_axi_arprot(S_AXI_0_1_ARPROT),
|
||||
.s_axi_arready(S_AXI_0_1_ARREADY),
|
||||
.s_axi_arsize(S_AXI_0_1_ARSIZE),
|
||||
.s_axi_arvalid(S_AXI_0_1_ARVALID),
|
||||
.s_axi_awaddr(S_AXI_0_1_AWADDR),
|
||||
.s_axi_awburst(S_AXI_0_1_AWBURST),
|
||||
.s_axi_awcache(S_AXI_0_1_AWCACHE),
|
||||
.s_axi_awlen(S_AXI_0_1_AWLEN),
|
||||
.s_axi_awlock(S_AXI_0_1_AWLOCK),
|
||||
.s_axi_awprot(S_AXI_0_1_AWPROT),
|
||||
.s_axi_awready(S_AXI_0_1_AWREADY),
|
||||
.s_axi_awsize(S_AXI_0_1_AWSIZE),
|
||||
.s_axi_awvalid(S_AXI_0_1_AWVALID),
|
||||
.s_axi_bready(S_AXI_0_1_BREADY),
|
||||
.s_axi_bresp(S_AXI_0_1_BRESP),
|
||||
.s_axi_bvalid(S_AXI_0_1_BVALID),
|
||||
.s_axi_rdata(S_AXI_0_1_RDATA),
|
||||
.s_axi_rlast(S_AXI_0_1_RLAST),
|
||||
.s_axi_rready(S_AXI_0_1_RREADY),
|
||||
.s_axi_rresp(S_AXI_0_1_RRESP),
|
||||
.s_axi_rvalid(S_AXI_0_1_RVALID),
|
||||
.s_axi_wdata(S_AXI_0_1_WDATA),
|
||||
.s_axi_wlast(S_AXI_0_1_WLAST),
|
||||
.s_axi_wready(S_AXI_0_1_WREADY),
|
||||
.s_axi_wstrb(S_AXI_0_1_WSTRB),
|
||||
.s_axi_wvalid(S_AXI_0_1_WVALID));
|
||||
ssp_combo_axi_datamover_0_0 axi_datamover_0
|
||||
(.m_axi_mm2s_aclk(aclk_0_1),
|
||||
.m_axi_mm2s_araddr(axi_datamover_0_M_AXI_MM2S_ARADDR),
|
||||
.m_axi_mm2s_arburst(axi_datamover_0_M_AXI_MM2S_ARBURST),
|
||||
.m_axi_mm2s_arcache(axi_datamover_0_M_AXI_MM2S_ARCACHE),
|
||||
.m_axi_mm2s_aresetn(aresetn_0_1),
|
||||
.m_axi_mm2s_arid(axi_datamover_0_M_AXI_MM2S_ARID),
|
||||
.m_axi_mm2s_arlen(axi_datamover_0_M_AXI_MM2S_ARLEN),
|
||||
.m_axi_mm2s_arprot(axi_datamover_0_M_AXI_MM2S_ARPROT),
|
||||
.m_axi_mm2s_arready(axi_datamover_0_M_AXI_MM2S_ARREADY),
|
||||
.m_axi_mm2s_arsize(axi_datamover_0_M_AXI_MM2S_ARSIZE),
|
||||
.m_axi_mm2s_aruser(axi_datamover_0_M_AXI_MM2S_ARUSER),
|
||||
.m_axi_mm2s_arvalid(axi_datamover_0_M_AXI_MM2S_ARVALID),
|
||||
.m_axi_mm2s_rdata(axi_datamover_0_M_AXI_MM2S_RDATA),
|
||||
.m_axi_mm2s_rlast(axi_datamover_0_M_AXI_MM2S_RLAST),
|
||||
.m_axi_mm2s_rready(axi_datamover_0_M_AXI_MM2S_RREADY),
|
||||
.m_axi_mm2s_rresp(axi_datamover_0_M_AXI_MM2S_RRESP),
|
||||
.m_axi_mm2s_rvalid(axi_datamover_0_M_AXI_MM2S_RVALID),
|
||||
.m_axi_s2mm_aclk(aclk_0_1),
|
||||
.m_axi_s2mm_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.m_axi_s2mm_awaddr(axi_datamover_0_M_AXI_S2MM_AWADDR),
|
||||
.m_axi_s2mm_awburst(axi_datamover_0_M_AXI_S2MM_AWBURST),
|
||||
.m_axi_s2mm_awcache(axi_datamover_0_M_AXI_S2MM_AWCACHE),
|
||||
.m_axi_s2mm_awid(axi_datamover_0_M_AXI_S2MM_AWID),
|
||||
.m_axi_s2mm_awlen(axi_datamover_0_M_AXI_S2MM_AWLEN),
|
||||
.m_axi_s2mm_awprot(axi_datamover_0_M_AXI_S2MM_AWPROT),
|
||||
.m_axi_s2mm_awready(axi_datamover_0_M_AXI_S2MM_AWREADY),
|
||||
.m_axi_s2mm_awsize(axi_datamover_0_M_AXI_S2MM_AWSIZE),
|
||||
.m_axi_s2mm_awuser(axi_datamover_0_M_AXI_S2MM_AWUSER),
|
||||
.m_axi_s2mm_awvalid(axi_datamover_0_M_AXI_S2MM_AWVALID),
|
||||
.m_axi_s2mm_bready(axi_datamover_0_M_AXI_S2MM_BREADY),
|
||||
.m_axi_s2mm_bresp(axi_datamover_0_M_AXI_S2MM_BRESP),
|
||||
.m_axi_s2mm_bvalid(axi_datamover_0_M_AXI_S2MM_BVALID),
|
||||
.m_axi_s2mm_wdata(axi_datamover_0_M_AXI_S2MM_WDATA),
|
||||
.m_axi_s2mm_wlast(axi_datamover_0_M_AXI_S2MM_WLAST),
|
||||
.m_axi_s2mm_wready(axi_datamover_0_M_AXI_S2MM_WREADY),
|
||||
.m_axi_s2mm_wstrb(axi_datamover_0_M_AXI_S2MM_WSTRB),
|
||||
.m_axi_s2mm_wvalid(axi_datamover_0_M_AXI_S2MM_WVALID),
|
||||
.m_axis_mm2s_cmdsts_aclk(aclk_0_1),
|
||||
.m_axis_mm2s_cmdsts_aresetn(aresetn_0_1),
|
||||
.m_axis_mm2s_sts_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
|
||||
.m_axis_mm2s_sts_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
|
||||
.m_axis_mm2s_sts_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
|
||||
.m_axis_mm2s_sts_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
|
||||
.m_axis_mm2s_sts_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID),
|
||||
.m_axis_mm2s_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
|
||||
.m_axis_mm2s_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
|
||||
.m_axis_mm2s_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
|
||||
.m_axis_mm2s_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
|
||||
.m_axis_mm2s_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID),
|
||||
.m_axis_s2mm_cmdsts_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.m_axis_s2mm_cmdsts_awclk(aclk_0_1),
|
||||
.m_axis_s2mm_sts_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
|
||||
.m_axis_s2mm_sts_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
|
||||
.m_axis_s2mm_sts_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
|
||||
.m_axis_s2mm_sts_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
|
||||
.m_axis_s2mm_sts_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID),
|
||||
.mm2s_err(axi_datamover_0_mm2s_err),
|
||||
.s2mm_err(axi_datamover_0_s2mm_err),
|
||||
.s_axis_mm2s_cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
|
||||
.s_axis_mm2s_cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
|
||||
.s_axis_mm2s_cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
|
||||
.s_axis_s2mm_cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
|
||||
.s_axis_s2mm_cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
|
||||
.s_axis_s2mm_cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
|
||||
.s_axis_s2mm_tdata(axis_data_fifo_0_M_AXIS_TDATA),
|
||||
.s_axis_s2mm_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
|
||||
.s_axis_s2mm_tlast(axis_data_fifo_0_M_AXIS_TLAST),
|
||||
.s_axis_s2mm_tready(axis_data_fifo_0_M_AXIS_TREADY),
|
||||
.s_axis_s2mm_tvalid(axis_data_fifo_0_M_AXIS_TVALID));
|
||||
ssp_combo_axil_reg_if_0_0 axil_reg_if_0
|
||||
(.aclk(aclk_0_1),
|
||||
.aresetn(aresetn_0_1),
|
||||
.reg_rd_ack(regfile_0_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_0_reg_rd_addr),
|
||||
.reg_rd_data(regfile_0_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_0_reg_rd_en),
|
||||
.reg_rd_wait(regfile_0_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_0_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_0_reg_wr_addr),
|
||||
.reg_wr_data(axil_reg_if_0_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_0_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_0_reg_wr_wait),
|
||||
.s_axil_araddr(s_axil_0_1_ARADDR),
|
||||
.s_axil_arprot(s_axil_0_1_ARPROT),
|
||||
.s_axil_arready(s_axil_0_1_ARREADY),
|
||||
.s_axil_arvalid(s_axil_0_1_ARVALID),
|
||||
.s_axil_awaddr(s_axil_0_1_AWADDR),
|
||||
.s_axil_awprot(s_axil_0_1_AWPROT),
|
||||
.s_axil_awready(s_axil_0_1_AWREADY),
|
||||
.s_axil_awvalid(s_axil_0_1_AWVALID),
|
||||
.s_axil_bready(s_axil_0_1_BREADY),
|
||||
.s_axil_bresp(s_axil_0_1_BRESP),
|
||||
.s_axil_bvalid(s_axil_0_1_BVALID),
|
||||
.s_axil_rdata(s_axil_0_1_RDATA),
|
||||
.s_axil_rready(s_axil_0_1_RREADY),
|
||||
.s_axil_rresp(s_axil_0_1_RRESP),
|
||||
.s_axil_rvalid(s_axil_0_1_RVALID),
|
||||
.s_axil_wdata(s_axil_0_1_WDATA),
|
||||
.s_axil_wready(s_axil_0_1_WREADY),
|
||||
.s_axil_wstrb(s_axil_0_1_WSTRB),
|
||||
.s_axil_wvalid(s_axil_0_1_WVALID));
|
||||
ssp_combo_axil_reg_if_1_0 axil_reg_if_1
|
||||
(.aclk(aclk_0_1),
|
||||
.aresetn(aresetn_0_1),
|
||||
.reg_rd_ack(regfile_1_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_1_reg_rd_addr),
|
||||
.reg_rd_data(regfile_1_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_1_reg_rd_en),
|
||||
.reg_rd_wait(regfile_1_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_1_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_1_reg_wr_addr),
|
||||
.reg_wr_data(axil_reg_if_1_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_1_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_1_reg_wr_wait),
|
||||
.s_axil_araddr(s_axil_0_2_ARADDR),
|
||||
.s_axil_arprot(s_axil_0_2_ARPROT),
|
||||
.s_axil_arready(s_axil_0_2_ARREADY),
|
||||
.s_axil_arvalid(s_axil_0_2_ARVALID),
|
||||
.s_axil_awaddr(s_axil_0_2_AWADDR),
|
||||
.s_axil_awprot(s_axil_0_2_AWPROT),
|
||||
.s_axil_awready(s_axil_0_2_AWREADY),
|
||||
.s_axil_awvalid(s_axil_0_2_AWVALID),
|
||||
.s_axil_bready(s_axil_0_2_BREADY),
|
||||
.s_axil_bresp(s_axil_0_2_BRESP),
|
||||
.s_axil_bvalid(s_axil_0_2_BVALID),
|
||||
.s_axil_rdata(s_axil_0_2_RDATA),
|
||||
.s_axil_rready(s_axil_0_2_RREADY),
|
||||
.s_axil_rresp(s_axil_0_2_RRESP),
|
||||
.s_axil_rvalid(s_axil_0_2_RVALID),
|
||||
.s_axil_wdata(s_axil_0_2_WDATA),
|
||||
.s_axil_wready(s_axil_0_2_WREADY),
|
||||
.s_axil_wstrb(s_axil_0_2_WSTRB),
|
||||
.s_axil_wvalid(s_axil_0_2_WVALID));
|
||||
ssp_combo_axis_data_fifo_0_0 axis_data_fifo_0
|
||||
(.m_axis_tdata(axis_data_fifo_0_M_AXIS_TDATA),
|
||||
.m_axis_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
|
||||
.m_axis_tlast(axis_data_fifo_0_M_AXIS_TLAST),
|
||||
.m_axis_tready(axis_data_fifo_0_M_AXIS_TREADY),
|
||||
.m_axis_tvalid(axis_data_fifo_0_M_AXIS_TVALID),
|
||||
.s_axis_aclk(aclk_0_1),
|
||||
.s_axis_aresetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.s_axis_tdata(stream_rx_ctrl_0_egress_TDATA),
|
||||
.s_axis_tkeep(stream_rx_ctrl_0_egress_TKEEP),
|
||||
.s_axis_tlast(stream_rx_ctrl_0_egress_TLAST),
|
||||
.s_axis_tready(stream_rx_ctrl_0_egress_TREADY),
|
||||
.s_axis_tstrb(stream_rx_ctrl_0_egress_TSTRB),
|
||||
.s_axis_tvalid(stream_rx_ctrl_0_egress_TVALID));
|
||||
ssp_combo_axis_data_fifo_1_0 axis_data_fifo_1
|
||||
(.m_axis_tdata(axis_data_fifo_1_M_AXIS_TDATA),
|
||||
.m_axis_tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
|
||||
.m_axis_tlast(axis_data_fifo_1_M_AXIS_TLAST),
|
||||
.m_axis_tready(axis_data_fifo_1_M_AXIS_TREADY),
|
||||
.m_axis_tvalid(axis_data_fifo_1_M_AXIS_TVALID),
|
||||
.s_axis_aclk(aclk_0_1),
|
||||
.s_axis_aresetn(aresetn_0_1),
|
||||
.s_axis_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
|
||||
.s_axis_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
|
||||
.s_axis_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
|
||||
.s_axis_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
|
||||
.s_axis_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID));
|
||||
ssp_combo_blk_mem_gen_0_0 blk_mem_gen_0
|
||||
(.addra(xlslice_0_Dout),
|
||||
.addrb(stream_tx_ctrl_0_desc_if_ADDR),
|
||||
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
|
||||
.clkb(stream_tx_ctrl_0_desc_if_CLK),
|
||||
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
|
||||
.dinb(stream_tx_ctrl_0_desc_if_DIN),
|
||||
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
|
||||
.doutb(stream_tx_ctrl_0_desc_if_DOUT),
|
||||
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
|
||||
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
|
||||
.web(stream_tx_ctrl_0_desc_if_WE));
|
||||
ssp_combo_regfile_0_0 regfile_0
|
||||
(.clk(aclk_0_1),
|
||||
.reg_0(regfile_0_reg_0),
|
||||
.reg_1(regfile_0_reg_1),
|
||||
.reg_2(regfile_0_reg_2),
|
||||
.reg_3(regfile_0_reg_3),
|
||||
.reg_4(regfile_0_reg_4),
|
||||
.reg_5(regfile_0_reg_5),
|
||||
.reg_6(regfile_0_reg_6),
|
||||
.reg_rd_ack(regfile_0_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_0_reg_rd_addr[7:0]),
|
||||
.reg_rd_data(regfile_0_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_0_reg_rd_en),
|
||||
.reg_rd_wait(regfile_0_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_0_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_0_reg_wr_addr[7:0]),
|
||||
.reg_wr_data(axil_reg_if_0_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_0_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_0_reg_wr_wait),
|
||||
.resetn(aresetn_0_1),
|
||||
.status_0(stream_rx_ctrl_0_status_00),
|
||||
.status_1(stream_rx_ctrl_0_status_01),
|
||||
.status_10(ssp_rx_0_status_02),
|
||||
.status_11(ssp_rx_0_status_03),
|
||||
.status_12(ssp_rx_0_status_04),
|
||||
.status_13(ssp_rx_0_status_05),
|
||||
.status_14(ssp_rx_0_status_06),
|
||||
.status_15(ssp_rx_0_status_07),
|
||||
.status_2(stream_rx_ctrl_0_status_02),
|
||||
.status_3(stream_rx_ctrl_0_status_03),
|
||||
.status_4(stream_rx_ctrl_0_status_04),
|
||||
.status_5(stream_rx_ctrl_0_status_05),
|
||||
.status_6(stream_rx_ctrl_0_status_06),
|
||||
.status_7(stream_rx_ctrl_0_status_07),
|
||||
.status_8(ssp_rx_0_status_00),
|
||||
.status_9(ssp_rx_0_status_01));
|
||||
ssp_combo_regfile_1_0 regfile_1
|
||||
(.clk(aclk_0_1),
|
||||
.reg_0(regfile_1_reg_0),
|
||||
.reg_1(regfile_1_reg_1),
|
||||
.reg_2(regfile_1_reg_2),
|
||||
.reg_3(regfile_1_reg_3),
|
||||
.reg_4(regfile_1_reg_4),
|
||||
.reg_rd_ack(regfile_1_reg_rd_ack),
|
||||
.reg_rd_addr(axil_reg_if_1_reg_rd_addr[7:0]),
|
||||
.reg_rd_data(regfile_1_reg_rd_data),
|
||||
.reg_rd_en(axil_reg_if_1_reg_rd_en),
|
||||
.reg_rd_wait(regfile_1_reg_rd_wait),
|
||||
.reg_wr_ack(regfile_1_reg_wr_ack),
|
||||
.reg_wr_addr(axil_reg_if_1_reg_wr_addr[7:0]),
|
||||
.reg_wr_data(axil_reg_if_1_reg_wr_data),
|
||||
.reg_wr_en(axil_reg_if_1_reg_wr_en),
|
||||
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
|
||||
.reg_wr_wait(regfile_1_reg_wr_wait),
|
||||
.resetn(aresetn_0_1),
|
||||
.status_0(stream_tx_ctrl_0_status_00),
|
||||
.status_1(stream_tx_ctrl_0_status_01),
|
||||
.status_10(ssp_tx_0_status_02),
|
||||
.status_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.status_2(stream_tx_ctrl_0_status_02),
|
||||
.status_3(stream_tx_ctrl_0_status_03),
|
||||
.status_4(stream_tx_ctrl_0_status_04),
|
||||
.status_5(ssp_tx_0_tx_data_count),
|
||||
.status_6(ssp_tx_0_tx_last_count),
|
||||
.status_7(ssp_tx_0_status),
|
||||
.status_8(ssp_tx_0_status_00),
|
||||
.status_9(ssp_tx_0_status_01));
|
||||
ssp_combo_ssp_rx_0_0 ssp_rx_0
|
||||
(.aresetn(aresetn_0_1),
|
||||
.clk(aclk_0_1),
|
||||
.config_00(regfile_0_reg_4),
|
||||
.config_01(regfile_0_reg_5),
|
||||
.config_02(regfile_0_reg_6),
|
||||
.enable(stream_rx_ctrl_0_enable),
|
||||
.ssp_clk(ssp_clk_0_1),
|
||||
.ssp_csn(ssp_csn_0_1),
|
||||
.ssp_data(ssp_data_0_1),
|
||||
.status_00(ssp_rx_0_status_00),
|
||||
.status_01(ssp_rx_0_status_01),
|
||||
.status_02(ssp_rx_0_status_02),
|
||||
.status_03(ssp_rx_0_status_03),
|
||||
.status_04(ssp_rx_0_status_04),
|
||||
.status_05(ssp_rx_0_status_05),
|
||||
.status_06(ssp_rx_0_status_06),
|
||||
.status_07(ssp_rx_0_status_07),
|
||||
.tdata(ssp_rx_0_interface_axis_TDATA),
|
||||
.tkeep(ssp_rx_0_interface_axis_TKEEP),
|
||||
.tlast(ssp_rx_0_interface_axis_TLAST),
|
||||
.tready(ssp_rx_0_interface_axis_TREADY),
|
||||
.tstrb(ssp_rx_0_interface_axis_TSTRB),
|
||||
.tvalid(ssp_rx_0_interface_axis_TVALID));
|
||||
ssp_combo_ssp_tx_0_0 ssp_tx_0
|
||||
(.aresetn(aresetn_0_1),
|
||||
.clk(aclk_0_1),
|
||||
.config_00(regfile_1_reg_4),
|
||||
.ssp_clk(ssp_tx_0_ssp_clk),
|
||||
.ssp_csn(ssp_tx_0_ssp_csn),
|
||||
.ssp_data(ssp_tx_0_ssp_data),
|
||||
.status_00(ssp_tx_0_status_00),
|
||||
.status_01(ssp_tx_0_status_01),
|
||||
.status_02(ssp_tx_0_status_02),
|
||||
.tdata(axis_data_fifo_1_M_AXIS_TDATA),
|
||||
.tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
|
||||
.tlast(axis_data_fifo_1_M_AXIS_TLAST),
|
||||
.tready(axis_data_fifo_1_M_AXIS_TREADY),
|
||||
.tstrb(1'b1),
|
||||
.tvalid(axis_data_fifo_1_M_AXIS_TVALID));
|
||||
ssp_combo_stream_rx_ctrl_0_0 stream_rx_ctrl_0
|
||||
(.clk(aclk_0_1),
|
||||
.cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
|
||||
.cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
|
||||
.cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
|
||||
.config_00(regfile_0_reg_0),
|
||||
.config_01(regfile_0_reg_1),
|
||||
.config_02(regfile_0_reg_2),
|
||||
.config_03(regfile_0_reg_3),
|
||||
.egress_tdata(stream_rx_ctrl_0_egress_TDATA),
|
||||
.egress_tkeep(stream_rx_ctrl_0_egress_TKEEP),
|
||||
.egress_tlast(stream_rx_ctrl_0_egress_TLAST),
|
||||
.egress_tready(stream_rx_ctrl_0_egress_TREADY),
|
||||
.egress_tstrb(stream_rx_ctrl_0_egress_TSTRB),
|
||||
.egress_tvalid(stream_rx_ctrl_0_egress_TVALID),
|
||||
.enable(stream_rx_ctrl_0_enable),
|
||||
.ingress_tdata(ssp_rx_0_interface_axis_TDATA),
|
||||
.ingress_tkeep(ssp_rx_0_interface_axis_TKEEP),
|
||||
.ingress_tlast(ssp_rx_0_interface_axis_TLAST),
|
||||
.ingress_tready(ssp_rx_0_interface_axis_TREADY),
|
||||
.ingress_tstrb(ssp_rx_0_interface_axis_TSTRB),
|
||||
.ingress_tvalid(ssp_rx_0_interface_axis_TVALID),
|
||||
.rst_n(aresetn_0_1),
|
||||
.s2mm_err(axi_datamover_0_s2mm_err),
|
||||
.s2mm_resetn(stream_rx_ctrl_0_s2mm_resetn),
|
||||
.status_00(stream_rx_ctrl_0_status_00),
|
||||
.status_01(stream_rx_ctrl_0_status_01),
|
||||
.status_02(stream_rx_ctrl_0_status_02),
|
||||
.status_03(stream_rx_ctrl_0_status_03),
|
||||
.status_04(stream_rx_ctrl_0_status_04),
|
||||
.status_05(stream_rx_ctrl_0_status_05),
|
||||
.status_06(stream_rx_ctrl_0_status_06),
|
||||
.status_07(stream_rx_ctrl_0_status_07),
|
||||
.status_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
|
||||
.status_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
|
||||
.status_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
|
||||
.status_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
|
||||
.status_tstrb({1'b1,1'b1,1'b1,1'b1}),
|
||||
.status_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID));
|
||||
ssp_combo_stream_tx_ctrl_0_0 stream_tx_ctrl_0
|
||||
(.clk(aclk_0_1),
|
||||
.cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
|
||||
.cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
|
||||
.cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
|
||||
.config_00(regfile_1_reg_0),
|
||||
.config_01(regfile_1_reg_1),
|
||||
.config_02(regfile_1_reg_2),
|
||||
.config_03(regfile_1_reg_3),
|
||||
.desc_addr(stream_tx_ctrl_0_desc_if_ADDR),
|
||||
.desc_clk(stream_tx_ctrl_0_desc_if_CLK),
|
||||
.desc_rdata(stream_tx_ctrl_0_desc_if_DOUT),
|
||||
.desc_wdata(stream_tx_ctrl_0_desc_if_DIN),
|
||||
.desc_we(stream_tx_ctrl_0_desc_if_WE),
|
||||
.mm2s_err(axi_datamover_0_mm2s_err),
|
||||
.rst_n(aresetn_0_1),
|
||||
.status_00(stream_tx_ctrl_0_status_00),
|
||||
.status_01(stream_tx_ctrl_0_status_01),
|
||||
.status_02(stream_tx_ctrl_0_status_02),
|
||||
.status_03(stream_tx_ctrl_0_status_03),
|
||||
.status_04(stream_tx_ctrl_0_status_04),
|
||||
.status_05(ssp_tx_0_tx_data_count),
|
||||
.status_06(ssp_tx_0_tx_last_count),
|
||||
.status_07(ssp_tx_0_status),
|
||||
.status_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
|
||||
.status_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
|
||||
.status_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
|
||||
.status_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
|
||||
.status_tstrb(1'b1),
|
||||
.status_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID));
|
||||
ssp_combo_xlslice_0_0 xlslice_0
|
||||
(.Din(axi_bram_ctrl_0_bram_addr_a[13:0]),
|
||||
.Dout(xlslice_0_Dout));
|
||||
endmodule
|
||||
@@ -0,0 +1,257 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axi_bram_ctrl_0_0",
|
||||
"cell_name": "axi_bram_ctrl_0",
|
||||
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_DEPTH": [ { "value": "4096", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MEMORY_DEPTH": [ { "value": "4096", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BRAM_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"bram_rst_a": [ { "direction": "out" } ],
|
||||
"bram_clk_a": [ { "direction": "out" } ],
|
||||
"bram_en_a": [ { "direction": "out" } ],
|
||||
"bram_we_a": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"bram_addr_a": [ { "direction": "out", "size_left": "14", "size_right": "0" } ],
|
||||
"bram_wrdata_a": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"bram_rddata_a": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_a" } ],
|
||||
"CLK": [ { "physical_name": "bram_clk_a" } ],
|
||||
"DIN": [ { "physical_name": "bram_wrdata_a" } ],
|
||||
"DOUT": [ { "physical_name": "bram_rddata_a" } ],
|
||||
"EN": [ { "physical_name": "bram_en_a" } ],
|
||||
"RST": [ { "physical_name": "bram_rst_a" } ],
|
||||
"WE": [ { "physical_name": "bram_we_a" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "8192",
|
||||
"display_name": "Mem0",
|
||||
"description": "Register Block",
|
||||
"usage": "memory",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,592 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axi_datamover_0_0",
|
||||
"cell_name": "axi_datamover_0",
|
||||
"component_reference": "xilinx.com:ip:axi_datamover:5.1",
|
||||
"ip_revision": "31",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ssp_combo_axi_datamover_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_include_mm2s": [ { "value": "Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_mm2s_stscmd_is_async": [ { "value": "false", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_data_width": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axis_mm2s_tdata_width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s_dre": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_mm2s_burst_size": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_mm2s_stsfifo": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"c_mm2s_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_btt_used": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_mm2s_addr_pipe_depth": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm": [ { "value": "Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_s2mm_stscmd_is_async": [ { "value": "false", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"c_m_axi_s2mm_data_width": [ { "value": "128", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s_axis_s2mm_tdata_width": [ { "value": "8", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_dre": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_s2mm_burst_size": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_include_s2mm_stsfifo": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"c_s2mm_stscmd_fifo_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_btt_used": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_addr_pipe_depth": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_s2mm_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_s2mm_support_indet_btt": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_mm2s_include_sf": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"c_s2mm_include_sf": [ { "value": "false", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"c_m_axi_mm2s_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_mm2s_arid": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_s2mm_id_width": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_m_axi_s2mm_awid": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_cache_user": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
|
||||
"c_enable_mm2s": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_s2mm": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_mm2s_adv_sig": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_enable_s2mm_adv_sig": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_addr_width": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_dummy": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"c_single_interface": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_INCLUDE_MM2S": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ARID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_MM2S_DATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_MM2S_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_STSFIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_MM2S_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MM2S_ADDR_PIPE_DEPTH": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_AWID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXI_S2MM_DATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_S2MM_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_STSFIFO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_STSCMD_FIFO_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_STSCMD_IS_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INCLUDE_S2MM_DRE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BURST_SIZE": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_BTT_USED": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_SUPPORT_INDET_BTT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_ADDR_PIPE_DEPTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MM2S_INCLUDE_SF": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S2MM_INCLUDE_SF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_CACHE_USER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MM2S_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_S2MM_TKEEP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_SKID_BUF": [ { "value": "11111", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_S2MM_ADV_SIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_MM2S_ADV_SIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CMD_WIDTH": [ { "value": "72", "resolve_type": "dependent", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "31" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"m_axi_mm2s_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mm2s_err": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_cmdsts_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axis_mm2s_cmdsts_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axis_mm2s_cmd_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_mm2s_cmd_tready": [ { "direction": "out" } ],
|
||||
"s_axis_mm2s_cmd_tdata": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_mm2s_sts_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_sts_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axis_mm2s_sts_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axis_mm2s_sts_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_mm2s_sts_tlast": [ { "direction": "out" } ],
|
||||
"m_axi_mm2s_arid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_mm2s_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_mm2s_aruser": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_mm2s_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_mm2s_arready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_mm2s_rready": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axis_mm2s_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_mm2s_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_mm2s_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s2mm_err": [ { "direction": "out" } ],
|
||||
"m_axis_s2mm_cmdsts_awclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axis_s2mm_cmdsts_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axis_s2mm_cmd_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_cmd_tready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_cmd_tdata": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_s2mm_sts_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_s2mm_sts_tready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axis_s2mm_sts_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axis_s2mm_sts_tkeep": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axis_s2mm_sts_tlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awlen": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awsize": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awburst": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awcache": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awuser": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_s2mm_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_awready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_wdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wstrb": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"m_axi_s2mm_wlast": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_s2mm_wready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"m_axi_s2mm_bready": [ { "direction": "out" } ],
|
||||
"s_axis_s2mm_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_s2mm_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axis_s2mm_tready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXI_MM2S": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_MM2S",
|
||||
"parameters": {
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "128", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "m_axi_mm2s_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "m_axi_mm2s_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "m_axi_mm2s_arcache" } ],
|
||||
"ARID": [ { "physical_name": "m_axi_mm2s_arid" } ],
|
||||
"ARLEN": [ { "physical_name": "m_axi_mm2s_arlen" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_mm2s_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_mm2s_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "m_axi_mm2s_arsize" } ],
|
||||
"ARUSER": [ { "physical_name": "m_axi_mm2s_aruser" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_mm2s_arvalid" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_mm2s_rdata" } ],
|
||||
"RLAST": [ { "physical_name": "m_axi_mm2s_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_mm2s_rready" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_mm2s_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_mm2s_rvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data_S2MM",
|
||||
"parameters": {
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "128", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
|
||||
"AWID": [ { "physical_name": "m_axi_s2mm_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
|
||||
"AWUSER": [ { "physical_name": "m_axi_s2mm_awuser" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_S2MM_CMD": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_s2mm_cmd_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_s2mm_cmd_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_s2mm_cmd_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_S2MM_STS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_s2mm_sts_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_s2mm_sts_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_s2mm_sts_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_s2mm_sts_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_s2mm_sts_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_MM2S_CMD": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_mm2s_cmd_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_mm2s_cmd_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_mm2s_cmd_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_MM2S_STS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_mm2s_sts_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_mm2s_sts_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_mm2s_sts_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_mm2s_sts_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_mm2s_sts_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_axi_mm2s_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_mm2s_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_axi_mm2s_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_axi_s2mm_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axi_s2mm_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_axi_s2mm_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_MM2S_CMDSTS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_MM2S_CMD:M_AXIS_MM2S_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_axis_mm2s_cmdsts_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_mm2s_cmdsts_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_MM2S_CMDSTS_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_axis_mm2s_cmdsts_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_S2MM_CMDSTS_AWCLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_S2MM_CMD:M_AXIS_S2MM_STS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_axis_s2mm_cmdsts_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_s2mm_cmdsts_awclk" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_S2MM_CMDSTS_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_axis_s2mm_cmdsts_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_MM2S": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_mm2s_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_mm2s_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_mm2s_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_mm2s_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_mm2s_tvalid" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"Data_MM2S": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
},
|
||||
"Data_S2MM": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axil_reg_if_0_0",
|
||||
"cell_name": "axil_reg_if_0",
|
||||
"component_reference": "xilinx.com:user:axil_reg_if:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TIMEOUT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_axil_reg_if_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"TIMEOUT": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axil_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_awready": [ { "direction": "out" } ],
|
||||
"s_axil_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axil_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_wready": [ { "direction": "out" } ],
|
||||
"s_axil_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axil_bvalid": [ { "direction": "out" } ],
|
||||
"s_axil_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_arready": [ { "direction": "out" } ],
|
||||
"s_axil_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axil_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axil_rvalid": [ { "direction": "out" } ],
|
||||
"s_axil_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"reg_wr_addr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_strb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"reg_wr_en": [ { "direction": "out" } ],
|
||||
"reg_wr_wait": [ { "direction": "in" } ],
|
||||
"reg_wr_ack": [ { "direction": "in" } ],
|
||||
"reg_rd_addr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_en": [ { "direction": "out" } ],
|
||||
"reg_rd_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_wait": [ { "direction": "in" } ],
|
||||
"reg_rd_ack": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axil": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axil",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axil_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axil_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axil_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axil_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axil_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axil_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axil_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axil_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axil_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axil_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axil_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axil_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axil_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axil_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axil_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axil_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axil_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axil_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axil_rready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axil", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axil": {
|
||||
"display_name": "s_axil",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x100000000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,189 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axil_reg_if_1_0",
|
||||
"cell_name": "axil_reg_if_1",
|
||||
"component_reference": "xilinx.com:user:axil_reg_if:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TIMEOUT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_axil_reg_if_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"TIMEOUT": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axil_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_awready": [ { "direction": "out" } ],
|
||||
"s_axil_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axil_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_wready": [ { "direction": "out" } ],
|
||||
"s_axil_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axil_bvalid": [ { "direction": "out" } ],
|
||||
"s_axil_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axil_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axil_arready": [ { "direction": "out" } ],
|
||||
"s_axil_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axil_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axil_rvalid": [ { "direction": "out" } ],
|
||||
"s_axil_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"reg_wr_addr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_strb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"reg_wr_en": [ { "direction": "out" } ],
|
||||
"reg_wr_wait": [ { "direction": "in" } ],
|
||||
"reg_wr_ack": [ { "direction": "in" } ],
|
||||
"reg_rd_addr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_en": [ { "direction": "out" } ],
|
||||
"reg_rd_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_wait": [ { "direction": "in" } ],
|
||||
"reg_rd_ack": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axil": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axil",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axil_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axil_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axil_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axil_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axil_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axil_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axil_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axil_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axil_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axil_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axil_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axil_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axil_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axil_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axil_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axil_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axil_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axil_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axil_rready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axil", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axil": {
|
||||
"display_name": "s_axil",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x100000000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,188 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axis_data_fifo_0_0",
|
||||
"cell_name": "axis_data_fifo_0",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "4096", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_axis_data_fifo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000011111", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "4096", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||
"s_axis_tstrb": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axis_tstrb": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TSTRB": [ { "physical_name": "s_axis_tstrb" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TSTRB": [ { "physical_name": "m_axis_tstrb" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axis_aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_axis_aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,184 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_axis_data_fifo_1_0",
|
||||
"cell_name": "axis_data_fifo_1",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "4096", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_axis_data_fifo_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000011011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "4096", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
|
||||
"s_axis_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"m_axis_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "s_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TKEEP": [ { "physical_name": "m_axis_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axis_aresetn", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_axis_aclken", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,284 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_blk_mem_gen_0_0",
|
||||
"cell_name": "blk_mem_gen_0",
|
||||
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ssp_combo_blk_mem_gen_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Byte_Write_Enable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Byte_Size": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
|
||||
"Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Assume_Synchronous_Clk": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Width_A": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Depth_A": [ { "value": "2048", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Read_Width_A": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_A": [ { "value": "WRITE_FIRST", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Width_B": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Read_Width_B": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"Operating_Mode_B": [ { "value": "READ_FIRST", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_B": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Port_B_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
|
||||
"Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"use_bram_block": [ { "value": "Stand_Alone", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"MEM_FILE": [ { "value": "NONE", "value_src": "ip_propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"CTRL_ECC_ALGO": [ { "value": "NONE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
|
||||
"EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEM_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYTE_SIZE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INIT_FILE": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_A": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_A": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_A": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_A": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRA_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WEB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_MODE_B": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_WRITE_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WRITE_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADDRB_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_36K_BRAM": [ { "value": "4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 22.1652 mW", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ena": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"clkb": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"web": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
|
||||
"dinb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||
"doutb": [ { "direction": "out", "size_left": "63", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "32768", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "64", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"EN": [ { "physical_name": "ena" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTB": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addrb" } ],
|
||||
"CLK": [ { "physical_name": "clkb" } ],
|
||||
"DIN": [ { "physical_name": "dinb" } ],
|
||||
"DOUT": [ { "physical_name": "doutb" } ],
|
||||
"WE": [ { "physical_name": "web" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
12
ssp_combo/src/ssp_combo_ooc.xdc
Normal file
12
ssp_combo/src/ssp_combo_ooc.xdc
Normal file
@@ -0,0 +1,12 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
create_clock -name ssp_rx_clk -period 10 [get_ports ssp_rx_clk]
|
||||
|
||||
################################################################################
|
||||
119
ssp_combo/src/ssp_combo_regfile_0_0/ssp_combo_regfile_0_0.xci
Normal file
119
ssp_combo/src/ssp_combo_regfile_0_0/ssp_combo_regfile_0_0.xci
Normal file
@@ -0,0 +1,119 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_regfile_0_0",
|
||||
"cell_name": "regfile_0",
|
||||
"component_reference": "xilinx.com:user:regfile:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"ADDR_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_regfile_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"ADDR_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"reg_wr_addr": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"reg_wr_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_strb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"reg_wr_en": [ { "direction": "in" } ],
|
||||
"reg_wr_wait": [ { "direction": "out" } ],
|
||||
"reg_wr_ack": [ { "direction": "out" } ],
|
||||
"reg_rd_addr": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"reg_rd_en": [ { "direction": "in" } ],
|
||||
"reg_rd_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_wait": [ { "direction": "out" } ],
|
||||
"reg_rd_ack": [ { "direction": "out" } ],
|
||||
"reg_0": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_1": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_2": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_3": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_4": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_5": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_6": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_7": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_0": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_1": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_2": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_3": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_4": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_5": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_6": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_7": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_8": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_9": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_10": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_11": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_12": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_13": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_14": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_15": [ { "direction": "in", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"resetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
119
ssp_combo/src/ssp_combo_regfile_1_0/ssp_combo_regfile_1_0.xci
Normal file
119
ssp_combo/src/ssp_combo_regfile_1_0/ssp_combo_regfile_1_0.xci
Normal file
@@ -0,0 +1,119 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_regfile_1_0",
|
||||
"cell_name": "regfile_1",
|
||||
"component_reference": "xilinx.com:user:regfile:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"ADDR_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_regfile_1_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"ADDR_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STRB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"reg_wr_addr": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"reg_wr_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_wr_strb": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"reg_wr_en": [ { "direction": "in" } ],
|
||||
"reg_wr_wait": [ { "direction": "out" } ],
|
||||
"reg_wr_ack": [ { "direction": "out" } ],
|
||||
"reg_rd_addr": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"reg_rd_en": [ { "direction": "in" } ],
|
||||
"reg_rd_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_rd_wait": [ { "direction": "out" } ],
|
||||
"reg_rd_ack": [ { "direction": "out" } ],
|
||||
"reg_0": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_1": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_2": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_3": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_4": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_5": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_6": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"reg_7": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_0": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_1": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_2": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_3": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_4": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_5": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_6": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_7": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_8": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_9": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_10": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_11": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_12": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_13": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_14": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_15": [ { "direction": "in", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"resetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
151
ssp_combo/src/ssp_combo_ssp_rx_0_0/ssp_combo_ssp_rx_0_0.xci
Normal file
151
ssp_combo/src/ssp_combo_ssp_rx_0_0/ssp_combo_ssp_rx_0_0.xci
Normal file
@@ -0,0 +1,151 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_ssp_rx_0_0",
|
||||
"cell_name": "ssp_rx_0",
|
||||
"component_reference": "xilinx.com:user:ssp_rx:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSP_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_ssp_rx_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SSP_HZ": [ { "value": "10000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"enable": [ { "direction": "in" } ],
|
||||
"tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"tvalid": [ { "direction": "out" } ],
|
||||
"tkeep": [ { "direction": "out" } ],
|
||||
"tstrb": [ { "direction": "out" } ],
|
||||
"tlast": [ { "direction": "out" } ],
|
||||
"tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"ssp_clk": [ { "direction": "in" } ],
|
||||
"ssp_csn": [ { "direction": "in" } ],
|
||||
"ssp_data": [ { "direction": "in" } ],
|
||||
"config_00": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_01": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_02": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_00": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_01": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_02": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_03": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_04": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_05": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_06": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_07": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"interface_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "tlast" } ],
|
||||
"TVALID": [ { "physical_name": "tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "interface_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ssp_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_ssp_rx_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ssp_clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
142
ssp_combo/src/ssp_combo_ssp_tx_0_0/ssp_combo_ssp_tx_0_0.xci
Normal file
142
ssp_combo/src/ssp_combo_ssp_tx_0_0/ssp_combo_ssp_tx_0_0.xci
Normal file
@@ -0,0 +1,142 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_ssp_tx_0_0",
|
||||
"cell_name": "ssp_tx_0",
|
||||
"component_reference": "xilinx.com:user:ssp_tx:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SSP_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_ssp_tx_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SSP_HZ": [ { "value": "10000000", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"tvalid": [ { "direction": "in" } ],
|
||||
"tkeep": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"tstrb": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"tready": [ { "direction": "out" } ],
|
||||
"ssp_clk": [ { "direction": "out" } ],
|
||||
"ssp_csn": [ { "direction": "out" } ],
|
||||
"ssp_data": [ { "direction": "out" } ],
|
||||
"ssp_tx_busy": [ { "direction": "out" } ],
|
||||
"config_00": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_00": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_01": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_02": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"interface_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "tlast" } ],
|
||||
"TVALID": [ { "physical_name": "tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "interface_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ssp_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_ssp_tx_0_0_ssp_clk", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ssp_clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,258 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_stream_rx_ctrl_0_0",
|
||||
"cell_name": "stream_rx_ctrl_0",
|
||||
"component_reference": "xilinx.com:user:stream_rx_ctrl:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CHANNEL_INDEX": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BTT_WIDTH": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CMD_WIDTH": [ { "value": "72", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STATUS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_stream_rx_ctrl_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CHANNEL_INDEX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BTT_WIDTH": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CMD_WIDTH": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STATUS_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"rst_n": [ { "direction": "in" } ],
|
||||
"config_00": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_01": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_02": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_03": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_00": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_01": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_02": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_03": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_04": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_05": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_06": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_07": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s2mm_err": [ { "direction": "in" } ],
|
||||
"enable": [ { "direction": "out" } ],
|
||||
"update_ptr": [ { "direction": "out" } ],
|
||||
"s2mm_resetn": [ { "direction": "out" } ],
|
||||
"ingress_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"ingress_tvalid": [ { "direction": "in" } ],
|
||||
"ingress_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ingress_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"ingress_tstrb": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"ingress_tready": [ { "direction": "out" } ],
|
||||
"egress_tdata": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"egress_tvalid": [ { "direction": "out" } ],
|
||||
"egress_tlast": [ { "direction": "out" } ],
|
||||
"egress_tkeep": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"egress_tstrb": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"egress_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"cmd_tdata": [ { "direction": "out", "size_left": "71", "size_right": "0" } ],
|
||||
"cmd_tvalid": [ { "direction": "out" } ],
|
||||
"cmd_tlast": [ { "direction": "out" } ],
|
||||
"cmd_tkeep": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
|
||||
"cmd_tstrb": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
|
||||
"cmd_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"status_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"status_tvalid": [ { "direction": "in" } ],
|
||||
"status_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"status_tkeep": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"status_tstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"status_tready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"cmd": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "cmd_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "cmd_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "cmd_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "cmd_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "cmd_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "cmd_tready" } ]
|
||||
}
|
||||
},
|
||||
"egress": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "egress_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "egress_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "egress_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "egress_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "egress_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "egress_tready" } ]
|
||||
}
|
||||
},
|
||||
"ingress": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "ingress_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "ingress_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "ingress_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "ingress_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "ingress_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "ingress_tready" } ]
|
||||
}
|
||||
},
|
||||
"status": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "status_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "status_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "status_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "status_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "status_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "status_tready" } ]
|
||||
}
|
||||
},
|
||||
"rst_n": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "rst_n" } ]
|
||||
}
|
||||
},
|
||||
"s2mm_resetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s2mm_resetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "cmd:egress:ingress:status", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,222 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_stream_tx_ctrl_0_0",
|
||||
"cell_name": "stream_tx_ctrl_0",
|
||||
"component_reference": "xilinx.com:user:stream_tx_ctrl:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BRAM_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BTT_WIDTH": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CMD_WIDTH": [ { "value": "72", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STATUS_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DESC_IDX_WIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "ssp_combo_stream_tx_ctrl_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BRAM_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BTT_WIDTH": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CMD_WIDTH": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"STATUS_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DESC_IDX_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"rst_n": [ { "direction": "in" } ],
|
||||
"config_00": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_01": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_02": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"config_03": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"status_00": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_01": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_02": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_03": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_04": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_05": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_06": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"status_07": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"mm2s_err": [ { "direction": "in" } ],
|
||||
"cmd_tdata": [ { "direction": "out", "size_left": "71", "size_right": "0" } ],
|
||||
"cmd_tvalid": [ { "direction": "out" } ],
|
||||
"cmd_tlast": [ { "direction": "out" } ],
|
||||
"cmd_tkeep": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
|
||||
"cmd_tstrb": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
|
||||
"cmd_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"status_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"status_tvalid": [ { "direction": "in" } ],
|
||||
"status_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"status_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"status_tstrb": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"status_tready": [ { "direction": "out" } ],
|
||||
"desc_clk": [ { "direction": "out" } ],
|
||||
"desc_en": [ { "direction": "out" } ],
|
||||
"desc_we": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"desc_addr": [ { "direction": "out", "size_left": "10", "size_right": "0" } ],
|
||||
"desc_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
|
||||
"desc_rdata": [ { "direction": "in", "size_left": "63", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"cmd": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "cmd_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "cmd_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "cmd_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "cmd_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "cmd_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "cmd_tready" } ]
|
||||
}
|
||||
},
|
||||
"status": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "status_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "status_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "status_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "status_tlast" } ],
|
||||
"TVALID": [ { "physical_name": "status_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "status_tready" } ]
|
||||
}
|
||||
},
|
||||
"rst_n": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "rst_n" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "cmd:status", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "ssp_combo_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"desc_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "desc_clk" } ]
|
||||
}
|
||||
},
|
||||
"desc_if": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DIN": [ { "physical_name": "desc_wdata" } ],
|
||||
"EN": [ { "physical_name": "desc_en" } ],
|
||||
"DOUT": [ { "physical_name": "desc_rdata" } ],
|
||||
"CLK": [ { "physical_name": "desc_clk" } ],
|
||||
"WE": [ { "physical_name": "desc_we" } ],
|
||||
"ADDR": [ { "physical_name": "desc_addr" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,53 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ssp_combo_xlslice_0_0",
|
||||
"cell_name": "xlslice_0",
|
||||
"component_reference": "xilinx.com:ip:xlslice:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ssp_combo_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_WIDTH": [ { "value": "14", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DOUT_WIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DIN_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg484" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"Din": [ { "direction": "in", "size_left": "13", "size_right": "0" } ],
|
||||
"Dout": [ { "direction": "out", "size_left": "10", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
3
ssp_combo/tmp_edit_project.cache/wt/project.wpc
Normal file
3
ssp_combo/tmp_edit_project.cache/wt/project.wpc
Normal file
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:66
|
||||
eof:
|
||||
7
ssp_combo/tmp_edit_project.hw/tmp_edit_project.lpr
Normal file
7
ssp_combo/tmp_edit_project.hw/tmp_edit_project.lpr
Normal file
@@ -0,0 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
226
ssp_combo/tmp_edit_project.xpr
Normal file
226
ssp_combo/tmp_edit_project.xpr
Normal file
@@ -0,0 +1,226 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="c:/users/le/workspace/work/repo/fpga_design_ip/ssp_combo/tmp_edit_project.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b471a9e3e1d142a8b89a2464dccefd9d"/>
|
||||
<Option Name="Part" Val="xc7a200tfbg484-2"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../../../../Users/le/workspace/work/repo/FPGA_DESIGN_IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../../../../../Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_combo/src/design_1_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="Library" Val=""/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../../../../Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_combo/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopRTLFile" Val="$PPRDIR/../../../../../../../Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_combo/src/design_1_wrapper.v"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../../../../../../Users/le/workspace/work/repo/FPGA_DESIGN_IP/ssp_combo/src/ssp_card.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="Library" Val=""/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg484-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg484-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
10
ssp_combo/xgui/design_1_wrapper_v1_0.tcl
Normal file
10
ssp_combo/xgui/design_1_wrapper_v1_0.tcl
Normal file
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
10
ssp_combo/xgui/ssp_combo_v1_0.tcl
Normal file
10
ssp_combo/xgui/ssp_combo_v1_0.tcl
Normal file
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user