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2026-03-06 16:22:17 +08:00
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
//Date : Tue Feb 10 16:20:32 2026
//Host : le-ThinkStation running 64-bit major release (build 9200)
//Command : generate_target ssp_combo_channel_2.bd
//Design : ssp_combo_channel_2
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "ssp_combo_channel_2,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ssp_combo_channel_2,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "ssp_combo_channel_2.hwdef" *)
module ssp_combo_channel_2
(M_AXI_MM2S_araddr,
M_AXI_MM2S_arburst,
M_AXI_MM2S_arcache,
M_AXI_MM2S_arid,
M_AXI_MM2S_arlen,
M_AXI_MM2S_arprot,
M_AXI_MM2S_arready,
M_AXI_MM2S_arsize,
M_AXI_MM2S_aruser,
M_AXI_MM2S_arvalid,
M_AXI_MM2S_rdata,
M_AXI_MM2S_rlast,
M_AXI_MM2S_rready,
M_AXI_MM2S_rresp,
M_AXI_MM2S_rvalid,
M_AXI_S2MM_awaddr,
M_AXI_S2MM_awburst,
M_AXI_S2MM_awcache,
M_AXI_S2MM_awid,
M_AXI_S2MM_awlen,
M_AXI_S2MM_awprot,
M_AXI_S2MM_awready,
M_AXI_S2MM_awsize,
M_AXI_S2MM_awuser,
M_AXI_S2MM_awvalid,
M_AXI_S2MM_bready,
M_AXI_S2MM_bresp,
M_AXI_S2MM_bvalid,
M_AXI_S2MM_wdata,
M_AXI_S2MM_wlast,
M_AXI_S2MM_wready,
M_AXI_S2MM_wstrb,
M_AXI_S2MM_wvalid,
S_AXI_TXDESC_araddr,
S_AXI_TXDESC_arburst,
S_AXI_TXDESC_arcache,
S_AXI_TXDESC_arlen,
S_AXI_TXDESC_arlock,
S_AXI_TXDESC_arprot,
S_AXI_TXDESC_arready,
S_AXI_TXDESC_arsize,
S_AXI_TXDESC_arvalid,
S_AXI_TXDESC_awaddr,
S_AXI_TXDESC_awburst,
S_AXI_TXDESC_awcache,
S_AXI_TXDESC_awlen,
S_AXI_TXDESC_awlock,
S_AXI_TXDESC_awprot,
S_AXI_TXDESC_awready,
S_AXI_TXDESC_awsize,
S_AXI_TXDESC_awvalid,
S_AXI_TXDESC_bready,
S_AXI_TXDESC_bresp,
S_AXI_TXDESC_bvalid,
S_AXI_TXDESC_rdata,
S_AXI_TXDESC_rlast,
S_AXI_TXDESC_rready,
S_AXI_TXDESC_rresp,
S_AXI_TXDESC_rvalid,
S_AXI_TXDESC_wdata,
S_AXI_TXDESC_wlast,
S_AXI_TXDESC_wready,
S_AXI_TXDESC_wstrb,
S_AXI_TXDESC_wvalid,
aresetn,
clk,
s_axil_rx_araddr,
s_axil_rx_arprot,
s_axil_rx_arready,
s_axil_rx_arvalid,
s_axil_rx_awaddr,
s_axil_rx_awprot,
s_axil_rx_awready,
s_axil_rx_awvalid,
s_axil_rx_bready,
s_axil_rx_bresp,
s_axil_rx_bvalid,
s_axil_rx_rdata,
s_axil_rx_rready,
s_axil_rx_rresp,
s_axil_rx_rvalid,
s_axil_rx_wdata,
s_axil_rx_wready,
s_axil_rx_wstrb,
s_axil_rx_wvalid,
s_axil_tx_araddr,
s_axil_tx_arprot,
s_axil_tx_arready,
s_axil_tx_arvalid,
s_axil_tx_awaddr,
s_axil_tx_awprot,
s_axil_tx_awready,
s_axil_tx_awvalid,
s_axil_tx_bready,
s_axil_tx_bresp,
s_axil_tx_bvalid,
s_axil_tx_rdata,
s_axil_tx_rready,
s_axil_tx_rresp,
s_axil_tx_rvalid,
s_axil_tx_wdata,
s_axil_tx_wready,
s_axil_tx_wstrb,
s_axil_tx_wvalid,
ssp_rx_clk,
ssp_rx_csn,
ssp_rx_data,
ssp_tx_clk,
ssp_tx_csn,
ssp_tx_data);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_MM2S, ADDR_WIDTH 32, ARUSER_WIDTH 4, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 0, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 0, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_MM2S_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST" *) output [1:0]M_AXI_MM2S_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE" *) output [3:0]M_AXI_MM2S_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID" *) output [3:0]M_AXI_MM2S_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]M_AXI_MM2S_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT" *) output [2:0]M_AXI_MM2S_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY" *) input M_AXI_MM2S_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]M_AXI_MM2S_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER" *) output [3:0]M_AXI_MM2S_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID" *) output M_AXI_MM2S_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA" *) input [127:0]M_AXI_MM2S_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST" *) input M_AXI_MM2S_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY" *) output M_AXI_MM2S_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP" *) input [1:0]M_AXI_MM2S_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID" *) input M_AXI_MM2S_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_S2MM, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 4, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 0, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE WRITE_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_S2MM_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST" *) output [1:0]M_AXI_S2MM_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE" *) output [3:0]M_AXI_S2MM_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID" *) output [3:0]M_AXI_S2MM_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN" *) output [7:0]M_AXI_S2MM_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT" *) output [2:0]M_AXI_S2MM_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY" *) input M_AXI_S2MM_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE" *) output [2:0]M_AXI_S2MM_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER" *) output [3:0]M_AXI_S2MM_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID" *) output M_AXI_S2MM_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY" *) output M_AXI_S2MM_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP" *) input [1:0]M_AXI_S2MM_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID" *) input M_AXI_S2MM_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA" *) output [127:0]M_AXI_S2MM_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST" *) output M_AXI_S2MM_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY" *) input M_AXI_S2MM_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB" *) output [15:0]M_AXI_S2MM_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID" *) output M_AXI_S2MM_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_TXDESC, ADDR_WIDTH 15, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 64, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [14:0]S_AXI_TXDESC_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARBURST" *) input [1:0]S_AXI_TXDESC_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARCACHE" *) input [3:0]S_AXI_TXDESC_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLEN" *) input [7:0]S_AXI_TXDESC_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLOCK" *) input S_AXI_TXDESC_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARPROT" *) input [2:0]S_AXI_TXDESC_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARREADY" *) output S_AXI_TXDESC_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARSIZE" *) input [2:0]S_AXI_TXDESC_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARVALID" *) input S_AXI_TXDESC_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWADDR" *) input [14:0]S_AXI_TXDESC_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWBURST" *) input [1:0]S_AXI_TXDESC_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWCACHE" *) input [3:0]S_AXI_TXDESC_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLEN" *) input [7:0]S_AXI_TXDESC_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLOCK" *) input S_AXI_TXDESC_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWPROT" *) input [2:0]S_AXI_TXDESC_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWREADY" *) output S_AXI_TXDESC_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWSIZE" *) input [2:0]S_AXI_TXDESC_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWVALID" *) input S_AXI_TXDESC_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BREADY" *) input S_AXI_TXDESC_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BRESP" *) output [1:0]S_AXI_TXDESC_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BVALID" *) output S_AXI_TXDESC_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RDATA" *) output [63:0]S_AXI_TXDESC_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RLAST" *) output S_AXI_TXDESC_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RREADY" *) input S_AXI_TXDESC_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RRESP" *) output [1:0]S_AXI_TXDESC_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RVALID" *) output S_AXI_TXDESC_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WDATA" *) input [63:0]S_AXI_TXDESC_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WLAST" *) input S_AXI_TXDESC_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WREADY" *) output S_AXI_TXDESC_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WSTRB" *) input [7:0]S_AXI_TXDESC_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WVALID" *) input S_AXI_TXDESC_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXI_S2MM:S_AXI_TXDESC:s_axil_rx:s_axil_tx, ASSOCIATED_RESET aresetn, CLK_DOMAIN ssp_combo_channel_2_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_rx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_rx_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARPROT" *) input [2:0]s_axil_rx_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARREADY" *) output s_axil_rx_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARVALID" *) input s_axil_rx_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWADDR" *) input [31:0]s_axil_rx_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWPROT" *) input [2:0]s_axil_rx_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWREADY" *) output s_axil_rx_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWVALID" *) input s_axil_rx_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BREADY" *) input s_axil_rx_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BRESP" *) output [1:0]s_axil_rx_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BVALID" *) output s_axil_rx_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RDATA" *) output [31:0]s_axil_rx_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RREADY" *) input s_axil_rx_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RRESP" *) output [1:0]s_axil_rx_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RVALID" *) output s_axil_rx_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WDATA" *) input [31:0]s_axil_rx_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WREADY" *) output s_axil_rx_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WSTRB" *) input [3:0]s_axil_rx_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WVALID" *) input s_axil_rx_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_tx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_tx_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARPROT" *) input [2:0]s_axil_tx_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARREADY" *) output s_axil_tx_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARVALID" *) input s_axil_tx_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWADDR" *) input [31:0]s_axil_tx_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWPROT" *) input [2:0]s_axil_tx_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWREADY" *) output s_axil_tx_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWVALID" *) input s_axil_tx_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BREADY" *) input s_axil_tx_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BRESP" *) output [1:0]s_axil_tx_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BVALID" *) output s_axil_tx_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RDATA" *) output [31:0]s_axil_tx_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RREADY" *) input s_axil_tx_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RRESP" *) output [1:0]s_axil_tx_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RVALID" *) output s_axil_tx_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WDATA" *) input [31:0]s_axil_tx_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WREADY" *) output s_axil_tx_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WSTRB" *) input [3:0]s_axil_tx_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WVALID" *) input s_axil_tx_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_RX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_RX_CLK, CLK_DOMAIN ssp_combo_channel_2_ssp_rx_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input ssp_rx_clk;
input ssp_rx_csn;
input ssp_rx_data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_TX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_TX_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) output ssp_tx_clk;
output ssp_tx_csn;
output ssp_tx_data;
wire [14:0]S_AXI_0_1_ARADDR;
wire [1:0]S_AXI_0_1_ARBURST;
wire [3:0]S_AXI_0_1_ARCACHE;
wire [7:0]S_AXI_0_1_ARLEN;
wire S_AXI_0_1_ARLOCK;
wire [2:0]S_AXI_0_1_ARPROT;
wire S_AXI_0_1_ARREADY;
wire [2:0]S_AXI_0_1_ARSIZE;
wire S_AXI_0_1_ARVALID;
wire [14:0]S_AXI_0_1_AWADDR;
wire [1:0]S_AXI_0_1_AWBURST;
wire [3:0]S_AXI_0_1_AWCACHE;
wire [7:0]S_AXI_0_1_AWLEN;
wire S_AXI_0_1_AWLOCK;
wire [2:0]S_AXI_0_1_AWPROT;
wire S_AXI_0_1_AWREADY;
wire [2:0]S_AXI_0_1_AWSIZE;
wire S_AXI_0_1_AWVALID;
wire S_AXI_0_1_BREADY;
wire [1:0]S_AXI_0_1_BRESP;
wire S_AXI_0_1_BVALID;
wire [63:0]S_AXI_0_1_RDATA;
wire S_AXI_0_1_RLAST;
wire S_AXI_0_1_RREADY;
wire [1:0]S_AXI_0_1_RRESP;
wire S_AXI_0_1_RVALID;
wire [63:0]S_AXI_0_1_WDATA;
wire S_AXI_0_1_WLAST;
wire S_AXI_0_1_WREADY;
wire [7:0]S_AXI_0_1_WSTRB;
wire S_AXI_0_1_WVALID;
wire aclk_0_1;
wire aresetn_0_1;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire [7:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [14:0]axi_bram_ctrl_0_bram_addr_a;
wire [7:0]axi_datamover_0_M_AXIS_MM2S_STS_TDATA;
wire [0:0]axi_datamover_0_M_AXIS_MM2S_STS_TKEEP;
wire axi_datamover_0_M_AXIS_MM2S_STS_TLAST;
wire axi_datamover_0_M_AXIS_MM2S_STS_TREADY;
wire axi_datamover_0_M_AXIS_MM2S_STS_TVALID;
wire [7:0]axi_datamover_0_M_AXIS_MM2S_TDATA;
wire [0:0]axi_datamover_0_M_AXIS_MM2S_TKEEP;
wire axi_datamover_0_M_AXIS_MM2S_TLAST;
wire axi_datamover_0_M_AXIS_MM2S_TREADY;
wire axi_datamover_0_M_AXIS_MM2S_TVALID;
wire [31:0]axi_datamover_0_M_AXIS_S2MM_STS_TDATA;
wire [3:0]axi_datamover_0_M_AXIS_S2MM_STS_TKEEP;
wire axi_datamover_0_M_AXIS_S2MM_STS_TLAST;
wire axi_datamover_0_M_AXIS_S2MM_STS_TREADY;
wire axi_datamover_0_M_AXIS_S2MM_STS_TVALID;
wire [31:0]axi_datamover_0_M_AXI_MM2S_ARADDR;
wire [1:0]axi_datamover_0_M_AXI_MM2S_ARBURST;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARCACHE;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARID;
wire [7:0]axi_datamover_0_M_AXI_MM2S_ARLEN;
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARPROT;
wire axi_datamover_0_M_AXI_MM2S_ARREADY;
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARSIZE;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARUSER;
wire axi_datamover_0_M_AXI_MM2S_ARVALID;
wire [127:0]axi_datamover_0_M_AXI_MM2S_RDATA;
wire axi_datamover_0_M_AXI_MM2S_RLAST;
wire axi_datamover_0_M_AXI_MM2S_RREADY;
wire [1:0]axi_datamover_0_M_AXI_MM2S_RRESP;
wire axi_datamover_0_M_AXI_MM2S_RVALID;
wire [31:0]axi_datamover_0_M_AXI_S2MM_AWADDR;
wire [1:0]axi_datamover_0_M_AXI_S2MM_AWBURST;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWCACHE;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWID;
wire [7:0]axi_datamover_0_M_AXI_S2MM_AWLEN;
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWPROT;
wire axi_datamover_0_M_AXI_S2MM_AWREADY;
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWSIZE;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWUSER;
wire axi_datamover_0_M_AXI_S2MM_AWVALID;
wire axi_datamover_0_M_AXI_S2MM_BREADY;
wire [1:0]axi_datamover_0_M_AXI_S2MM_BRESP;
wire axi_datamover_0_M_AXI_S2MM_BVALID;
wire [127:0]axi_datamover_0_M_AXI_S2MM_WDATA;
wire axi_datamover_0_M_AXI_S2MM_WLAST;
wire axi_datamover_0_M_AXI_S2MM_WREADY;
wire [15:0]axi_datamover_0_M_AXI_S2MM_WSTRB;
wire axi_datamover_0_M_AXI_S2MM_WVALID;
wire axi_datamover_0_mm2s_err;
wire axi_datamover_0_s2mm_err;
wire [31:0]axil_reg_if_0_reg_rd_addr;
wire axil_reg_if_0_reg_rd_en;
wire [31:0]axil_reg_if_0_reg_wr_addr;
wire [31:0]axil_reg_if_0_reg_wr_data;
wire axil_reg_if_0_reg_wr_en;
wire [3:0]axil_reg_if_0_reg_wr_strb;
wire [31:0]axil_reg_if_1_reg_rd_addr;
wire axil_reg_if_1_reg_rd_en;
wire [31:0]axil_reg_if_1_reg_wr_addr;
wire [31:0]axil_reg_if_1_reg_wr_data;
wire axil_reg_if_1_reg_wr_en;
wire [3:0]axil_reg_if_1_reg_wr_strb;
wire [7:0]axis_data_fifo_0_M_AXIS_TDATA;
wire [0:0]axis_data_fifo_0_M_AXIS_TKEEP;
wire axis_data_fifo_0_M_AXIS_TLAST;
wire axis_data_fifo_0_M_AXIS_TREADY;
wire axis_data_fifo_0_M_AXIS_TVALID;
wire [7:0]axis_data_fifo_1_M_AXIS_TDATA;
wire [0:0]axis_data_fifo_1_M_AXIS_TKEEP;
wire axis_data_fifo_1_M_AXIS_TLAST;
wire axis_data_fifo_1_M_AXIS_TREADY;
wire axis_data_fifo_1_M_AXIS_TVALID;
wire [31:0]regfile_0_reg_0;
wire [31:0]regfile_0_reg_1;
wire [31:0]regfile_0_reg_2;
wire [31:0]regfile_0_reg_3;
wire [31:0]regfile_0_reg_4;
wire [31:0]regfile_0_reg_5;
wire [31:0]regfile_0_reg_6;
wire regfile_0_reg_rd_ack;
wire [31:0]regfile_0_reg_rd_data;
wire regfile_0_reg_rd_wait;
wire regfile_0_reg_wr_ack;
wire regfile_0_reg_wr_wait;
wire [31:0]regfile_1_reg_0;
wire [31:0]regfile_1_reg_1;
wire [31:0]regfile_1_reg_2;
wire [31:0]regfile_1_reg_3;
wire [31:0]regfile_1_reg_4;
wire [31:0]regfile_1_reg_5;
wire regfile_1_reg_rd_ack;
wire [31:0]regfile_1_reg_rd_data;
wire regfile_1_reg_rd_wait;
wire regfile_1_reg_wr_ack;
wire regfile_1_reg_wr_wait;
wire [31:0]s_axil_0_1_ARADDR;
wire [2:0]s_axil_0_1_ARPROT;
wire s_axil_0_1_ARREADY;
wire s_axil_0_1_ARVALID;
wire [31:0]s_axil_0_1_AWADDR;
wire [2:0]s_axil_0_1_AWPROT;
wire s_axil_0_1_AWREADY;
wire s_axil_0_1_AWVALID;
wire s_axil_0_1_BREADY;
wire [1:0]s_axil_0_1_BRESP;
wire s_axil_0_1_BVALID;
wire [31:0]s_axil_0_1_RDATA;
wire s_axil_0_1_RREADY;
wire [1:0]s_axil_0_1_RRESP;
wire s_axil_0_1_RVALID;
wire [31:0]s_axil_0_1_WDATA;
wire s_axil_0_1_WREADY;
wire [3:0]s_axil_0_1_WSTRB;
wire s_axil_0_1_WVALID;
wire [31:0]s_axil_0_2_ARADDR;
wire [2:0]s_axil_0_2_ARPROT;
wire s_axil_0_2_ARREADY;
wire s_axil_0_2_ARVALID;
wire [31:0]s_axil_0_2_AWADDR;
wire [2:0]s_axil_0_2_AWPROT;
wire s_axil_0_2_AWREADY;
wire s_axil_0_2_AWVALID;
wire s_axil_0_2_BREADY;
wire [1:0]s_axil_0_2_BRESP;
wire s_axil_0_2_BVALID;
wire [31:0]s_axil_0_2_RDATA;
wire s_axil_0_2_RREADY;
wire [1:0]s_axil_0_2_RRESP;
wire s_axil_0_2_RVALID;
wire [31:0]s_axil_0_2_WDATA;
wire s_axil_0_2_WREADY;
wire [3:0]s_axil_0_2_WSTRB;
wire s_axil_0_2_WVALID;
wire ssp_clk_0_1;
wire ssp_csn_0_1;
wire ssp_data_0_1;
wire [7:0]ssp_rx_0_interface_axis_TDATA;
wire ssp_rx_0_interface_axis_TKEEP;
wire ssp_rx_0_interface_axis_TLAST;
wire ssp_rx_0_interface_axis_TREADY;
wire ssp_rx_0_interface_axis_TSTRB;
wire ssp_rx_0_interface_axis_TVALID;
wire [31:0]ssp_rx_0_status_00;
wire [31:0]ssp_rx_0_status_01;
wire [31:0]ssp_rx_0_status_02;
wire [31:0]ssp_rx_0_status_03;
wire [31:0]ssp_rx_0_status_04;
wire [31:0]ssp_rx_0_status_05;
wire [31:0]ssp_rx_0_status_06;
wire [31:0]ssp_rx_0_status_07;
wire ssp_tx_0_ssp_clk;
wire ssp_tx_0_ssp_csn;
wire ssp_tx_0_ssp_data;
wire [31:0]ssp_tx_0_status;
wire [31:0]ssp_tx_0_status_00;
wire [31:0]ssp_tx_0_status_01;
wire [31:0]ssp_tx_0_status_02;
wire [31:0]ssp_tx_0_tx_data_count;
wire [31:0]ssp_tx_0_tx_last_count;
wire [71:0]stream_rx_ctrl_0_cmd_TDATA;
wire stream_rx_ctrl_0_cmd_TREADY;
wire stream_rx_ctrl_0_cmd_TVALID;
wire [7:0]stream_rx_ctrl_0_egress_TDATA;
wire [0:0]stream_rx_ctrl_0_egress_TKEEP;
wire stream_rx_ctrl_0_egress_TLAST;
wire stream_rx_ctrl_0_egress_TREADY;
wire [0:0]stream_rx_ctrl_0_egress_TSTRB;
wire stream_rx_ctrl_0_egress_TVALID;
wire stream_rx_ctrl_0_enable;
wire stream_rx_ctrl_0_s2mm_resetn;
wire [31:0]stream_rx_ctrl_0_status_00;
wire [31:0]stream_rx_ctrl_0_status_01;
wire [31:0]stream_rx_ctrl_0_status_02;
wire [31:0]stream_rx_ctrl_0_status_03;
wire [31:0]stream_rx_ctrl_0_status_04;
wire [31:0]stream_rx_ctrl_0_status_05;
wire [31:0]stream_rx_ctrl_0_status_06;
wire [31:0]stream_rx_ctrl_0_status_07;
wire [71:0]stream_tx_ctrl_0_cmd_TDATA;
wire stream_tx_ctrl_0_cmd_TREADY;
wire stream_tx_ctrl_0_cmd_TVALID;
wire [10:0]stream_tx_ctrl_0_desc_if_ADDR;
wire stream_tx_ctrl_0_desc_if_CLK;
wire [63:0]stream_tx_ctrl_0_desc_if_DIN;
wire [63:0]stream_tx_ctrl_0_desc_if_DOUT;
wire [7:0]stream_tx_ctrl_0_desc_if_WE;
wire stream_tx_ctrl_0_mm2s_resetn;
wire [31:0]stream_tx_ctrl_0_status_00;
wire [31:0]stream_tx_ctrl_0_status_01;
wire [31:0]stream_tx_ctrl_0_status_02;
wire [31:0]stream_tx_ctrl_0_status_03;
wire [31:0]stream_tx_ctrl_0_status_04;
wire [10:0]xlslice_0_Dout;
assign M_AXI_MM2S_araddr[31:0] = axi_datamover_0_M_AXI_MM2S_ARADDR;
assign M_AXI_MM2S_arburst[1:0] = axi_datamover_0_M_AXI_MM2S_ARBURST;
assign M_AXI_MM2S_arcache[3:0] = axi_datamover_0_M_AXI_MM2S_ARCACHE;
assign M_AXI_MM2S_arid[3:0] = axi_datamover_0_M_AXI_MM2S_ARID;
assign M_AXI_MM2S_arlen[7:0] = axi_datamover_0_M_AXI_MM2S_ARLEN;
assign M_AXI_MM2S_arprot[2:0] = axi_datamover_0_M_AXI_MM2S_ARPROT;
assign M_AXI_MM2S_arsize[2:0] = axi_datamover_0_M_AXI_MM2S_ARSIZE;
assign M_AXI_MM2S_aruser[3:0] = axi_datamover_0_M_AXI_MM2S_ARUSER;
assign M_AXI_MM2S_arvalid = axi_datamover_0_M_AXI_MM2S_ARVALID;
assign M_AXI_MM2S_rready = axi_datamover_0_M_AXI_MM2S_RREADY;
assign M_AXI_S2MM_awaddr[31:0] = axi_datamover_0_M_AXI_S2MM_AWADDR;
assign M_AXI_S2MM_awburst[1:0] = axi_datamover_0_M_AXI_S2MM_AWBURST;
assign M_AXI_S2MM_awcache[3:0] = axi_datamover_0_M_AXI_S2MM_AWCACHE;
assign M_AXI_S2MM_awid[3:0] = axi_datamover_0_M_AXI_S2MM_AWID;
assign M_AXI_S2MM_awlen[7:0] = axi_datamover_0_M_AXI_S2MM_AWLEN;
assign M_AXI_S2MM_awprot[2:0] = axi_datamover_0_M_AXI_S2MM_AWPROT;
assign M_AXI_S2MM_awsize[2:0] = axi_datamover_0_M_AXI_S2MM_AWSIZE;
assign M_AXI_S2MM_awuser[3:0] = axi_datamover_0_M_AXI_S2MM_AWUSER;
assign M_AXI_S2MM_awvalid = axi_datamover_0_M_AXI_S2MM_AWVALID;
assign M_AXI_S2MM_bready = axi_datamover_0_M_AXI_S2MM_BREADY;
assign M_AXI_S2MM_wdata[127:0] = axi_datamover_0_M_AXI_S2MM_WDATA;
assign M_AXI_S2MM_wlast = axi_datamover_0_M_AXI_S2MM_WLAST;
assign M_AXI_S2MM_wstrb[15:0] = axi_datamover_0_M_AXI_S2MM_WSTRB;
assign M_AXI_S2MM_wvalid = axi_datamover_0_M_AXI_S2MM_WVALID;
assign S_AXI_0_1_ARADDR = S_AXI_TXDESC_araddr[14:0];
assign S_AXI_0_1_ARBURST = S_AXI_TXDESC_arburst[1:0];
assign S_AXI_0_1_ARCACHE = S_AXI_TXDESC_arcache[3:0];
assign S_AXI_0_1_ARLEN = S_AXI_TXDESC_arlen[7:0];
assign S_AXI_0_1_ARLOCK = S_AXI_TXDESC_arlock;
assign S_AXI_0_1_ARPROT = S_AXI_TXDESC_arprot[2:0];
assign S_AXI_0_1_ARSIZE = S_AXI_TXDESC_arsize[2:0];
assign S_AXI_0_1_ARVALID = S_AXI_TXDESC_arvalid;
assign S_AXI_0_1_AWADDR = S_AXI_TXDESC_awaddr[14:0];
assign S_AXI_0_1_AWBURST = S_AXI_TXDESC_awburst[1:0];
assign S_AXI_0_1_AWCACHE = S_AXI_TXDESC_awcache[3:0];
assign S_AXI_0_1_AWLEN = S_AXI_TXDESC_awlen[7:0];
assign S_AXI_0_1_AWLOCK = S_AXI_TXDESC_awlock;
assign S_AXI_0_1_AWPROT = S_AXI_TXDESC_awprot[2:0];
assign S_AXI_0_1_AWSIZE = S_AXI_TXDESC_awsize[2:0];
assign S_AXI_0_1_AWVALID = S_AXI_TXDESC_awvalid;
assign S_AXI_0_1_BREADY = S_AXI_TXDESC_bready;
assign S_AXI_0_1_RREADY = S_AXI_TXDESC_rready;
assign S_AXI_0_1_WDATA = S_AXI_TXDESC_wdata[63:0];
assign S_AXI_0_1_WLAST = S_AXI_TXDESC_wlast;
assign S_AXI_0_1_WSTRB = S_AXI_TXDESC_wstrb[7:0];
assign S_AXI_0_1_WVALID = S_AXI_TXDESC_wvalid;
assign S_AXI_TXDESC_arready = S_AXI_0_1_ARREADY;
assign S_AXI_TXDESC_awready = S_AXI_0_1_AWREADY;
assign S_AXI_TXDESC_bresp[1:0] = S_AXI_0_1_BRESP;
assign S_AXI_TXDESC_bvalid = S_AXI_0_1_BVALID;
assign S_AXI_TXDESC_rdata[63:0] = S_AXI_0_1_RDATA;
assign S_AXI_TXDESC_rlast = S_AXI_0_1_RLAST;
assign S_AXI_TXDESC_rresp[1:0] = S_AXI_0_1_RRESP;
assign S_AXI_TXDESC_rvalid = S_AXI_0_1_RVALID;
assign S_AXI_TXDESC_wready = S_AXI_0_1_WREADY;
assign aclk_0_1 = clk;
assign aresetn_0_1 = aresetn;
assign axi_datamover_0_M_AXI_MM2S_ARREADY = M_AXI_MM2S_arready;
assign axi_datamover_0_M_AXI_MM2S_RDATA = M_AXI_MM2S_rdata[127:0];
assign axi_datamover_0_M_AXI_MM2S_RLAST = M_AXI_MM2S_rlast;
assign axi_datamover_0_M_AXI_MM2S_RRESP = M_AXI_MM2S_rresp[1:0];
assign axi_datamover_0_M_AXI_MM2S_RVALID = M_AXI_MM2S_rvalid;
assign axi_datamover_0_M_AXI_S2MM_AWREADY = M_AXI_S2MM_awready;
assign axi_datamover_0_M_AXI_S2MM_BRESP = M_AXI_S2MM_bresp[1:0];
assign axi_datamover_0_M_AXI_S2MM_BVALID = M_AXI_S2MM_bvalid;
assign axi_datamover_0_M_AXI_S2MM_WREADY = M_AXI_S2MM_wready;
assign s_axil_0_1_ARADDR = s_axil_rx_araddr[31:0];
assign s_axil_0_1_ARPROT = s_axil_rx_arprot[2:0];
assign s_axil_0_1_ARVALID = s_axil_rx_arvalid;
assign s_axil_0_1_AWADDR = s_axil_rx_awaddr[31:0];
assign s_axil_0_1_AWPROT = s_axil_rx_awprot[2:0];
assign s_axil_0_1_AWVALID = s_axil_rx_awvalid;
assign s_axil_0_1_BREADY = s_axil_rx_bready;
assign s_axil_0_1_RREADY = s_axil_rx_rready;
assign s_axil_0_1_WDATA = s_axil_rx_wdata[31:0];
assign s_axil_0_1_WSTRB = s_axil_rx_wstrb[3:0];
assign s_axil_0_1_WVALID = s_axil_rx_wvalid;
assign s_axil_0_2_ARADDR = s_axil_tx_araddr[31:0];
assign s_axil_0_2_ARPROT = s_axil_tx_arprot[2:0];
assign s_axil_0_2_ARVALID = s_axil_tx_arvalid;
assign s_axil_0_2_AWADDR = s_axil_tx_awaddr[31:0];
assign s_axil_0_2_AWPROT = s_axil_tx_awprot[2:0];
assign s_axil_0_2_AWVALID = s_axil_tx_awvalid;
assign s_axil_0_2_BREADY = s_axil_tx_bready;
assign s_axil_0_2_RREADY = s_axil_tx_rready;
assign s_axil_0_2_WDATA = s_axil_tx_wdata[31:0];
assign s_axil_0_2_WSTRB = s_axil_tx_wstrb[3:0];
assign s_axil_0_2_WVALID = s_axil_tx_wvalid;
assign s_axil_rx_arready = s_axil_0_1_ARREADY;
assign s_axil_rx_awready = s_axil_0_1_AWREADY;
assign s_axil_rx_bresp[1:0] = s_axil_0_1_BRESP;
assign s_axil_rx_bvalid = s_axil_0_1_BVALID;
assign s_axil_rx_rdata[31:0] = s_axil_0_1_RDATA;
assign s_axil_rx_rresp[1:0] = s_axil_0_1_RRESP;
assign s_axil_rx_rvalid = s_axil_0_1_RVALID;
assign s_axil_rx_wready = s_axil_0_1_WREADY;
assign s_axil_tx_arready = s_axil_0_2_ARREADY;
assign s_axil_tx_awready = s_axil_0_2_AWREADY;
assign s_axil_tx_bresp[1:0] = s_axil_0_2_BRESP;
assign s_axil_tx_bvalid = s_axil_0_2_BVALID;
assign s_axil_tx_rdata[31:0] = s_axil_0_2_RDATA;
assign s_axil_tx_rresp[1:0] = s_axil_0_2_RRESP;
assign s_axil_tx_rvalid = s_axil_0_2_RVALID;
assign s_axil_tx_wready = s_axil_0_2_WREADY;
assign ssp_clk_0_1 = ssp_rx_clk;
assign ssp_csn_0_1 = ssp_rx_csn;
assign ssp_data_0_1 = ssp_rx_data;
assign ssp_tx_clk = ssp_tx_0_ssp_clk;
assign ssp_tx_csn = ssp_tx_0_ssp_csn;
assign ssp_tx_data = ssp_tx_0_ssp_data;
ssp_combo_channel_2_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_bram_addr_a),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(aclk_0_1),
.s_axi_araddr(S_AXI_0_1_ARADDR),
.s_axi_arburst(S_AXI_0_1_ARBURST),
.s_axi_arcache(S_AXI_0_1_ARCACHE),
.s_axi_aresetn(aresetn_0_1),
.s_axi_arlen(S_AXI_0_1_ARLEN),
.s_axi_arlock(S_AXI_0_1_ARLOCK),
.s_axi_arprot(S_AXI_0_1_ARPROT),
.s_axi_arready(S_AXI_0_1_ARREADY),
.s_axi_arsize(S_AXI_0_1_ARSIZE),
.s_axi_arvalid(S_AXI_0_1_ARVALID),
.s_axi_awaddr(S_AXI_0_1_AWADDR),
.s_axi_awburst(S_AXI_0_1_AWBURST),
.s_axi_awcache(S_AXI_0_1_AWCACHE),
.s_axi_awlen(S_AXI_0_1_AWLEN),
.s_axi_awlock(S_AXI_0_1_AWLOCK),
.s_axi_awprot(S_AXI_0_1_AWPROT),
.s_axi_awready(S_AXI_0_1_AWREADY),
.s_axi_awsize(S_AXI_0_1_AWSIZE),
.s_axi_awvalid(S_AXI_0_1_AWVALID),
.s_axi_bready(S_AXI_0_1_BREADY),
.s_axi_bresp(S_AXI_0_1_BRESP),
.s_axi_bvalid(S_AXI_0_1_BVALID),
.s_axi_rdata(S_AXI_0_1_RDATA),
.s_axi_rlast(S_AXI_0_1_RLAST),
.s_axi_rready(S_AXI_0_1_RREADY),
.s_axi_rresp(S_AXI_0_1_RRESP),
.s_axi_rvalid(S_AXI_0_1_RVALID),
.s_axi_wdata(S_AXI_0_1_WDATA),
.s_axi_wlast(S_AXI_0_1_WLAST),
.s_axi_wready(S_AXI_0_1_WREADY),
.s_axi_wstrb(S_AXI_0_1_WSTRB),
.s_axi_wvalid(S_AXI_0_1_WVALID));
ssp_combo_channel_2_axi_datamover_0_0 axi_datamover_0
(.m_axi_mm2s_aclk(aclk_0_1),
.m_axi_mm2s_araddr(axi_datamover_0_M_AXI_MM2S_ARADDR),
.m_axi_mm2s_arburst(axi_datamover_0_M_AXI_MM2S_ARBURST),
.m_axi_mm2s_arcache(axi_datamover_0_M_AXI_MM2S_ARCACHE),
.m_axi_mm2s_aresetn(stream_tx_ctrl_0_mm2s_resetn),
.m_axi_mm2s_arid(axi_datamover_0_M_AXI_MM2S_ARID),
.m_axi_mm2s_arlen(axi_datamover_0_M_AXI_MM2S_ARLEN),
.m_axi_mm2s_arprot(axi_datamover_0_M_AXI_MM2S_ARPROT),
.m_axi_mm2s_arready(axi_datamover_0_M_AXI_MM2S_ARREADY),
.m_axi_mm2s_arsize(axi_datamover_0_M_AXI_MM2S_ARSIZE),
.m_axi_mm2s_aruser(axi_datamover_0_M_AXI_MM2S_ARUSER),
.m_axi_mm2s_arvalid(axi_datamover_0_M_AXI_MM2S_ARVALID),
.m_axi_mm2s_rdata(axi_datamover_0_M_AXI_MM2S_RDATA),
.m_axi_mm2s_rlast(axi_datamover_0_M_AXI_MM2S_RLAST),
.m_axi_mm2s_rready(axi_datamover_0_M_AXI_MM2S_RREADY),
.m_axi_mm2s_rresp(axi_datamover_0_M_AXI_MM2S_RRESP),
.m_axi_mm2s_rvalid(axi_datamover_0_M_AXI_MM2S_RVALID),
.m_axi_s2mm_aclk(aclk_0_1),
.m_axi_s2mm_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.m_axi_s2mm_awaddr(axi_datamover_0_M_AXI_S2MM_AWADDR),
.m_axi_s2mm_awburst(axi_datamover_0_M_AXI_S2MM_AWBURST),
.m_axi_s2mm_awcache(axi_datamover_0_M_AXI_S2MM_AWCACHE),
.m_axi_s2mm_awid(axi_datamover_0_M_AXI_S2MM_AWID),
.m_axi_s2mm_awlen(axi_datamover_0_M_AXI_S2MM_AWLEN),
.m_axi_s2mm_awprot(axi_datamover_0_M_AXI_S2MM_AWPROT),
.m_axi_s2mm_awready(axi_datamover_0_M_AXI_S2MM_AWREADY),
.m_axi_s2mm_awsize(axi_datamover_0_M_AXI_S2MM_AWSIZE),
.m_axi_s2mm_awuser(axi_datamover_0_M_AXI_S2MM_AWUSER),
.m_axi_s2mm_awvalid(axi_datamover_0_M_AXI_S2MM_AWVALID),
.m_axi_s2mm_bready(axi_datamover_0_M_AXI_S2MM_BREADY),
.m_axi_s2mm_bresp(axi_datamover_0_M_AXI_S2MM_BRESP),
.m_axi_s2mm_bvalid(axi_datamover_0_M_AXI_S2MM_BVALID),
.m_axi_s2mm_wdata(axi_datamover_0_M_AXI_S2MM_WDATA),
.m_axi_s2mm_wlast(axi_datamover_0_M_AXI_S2MM_WLAST),
.m_axi_s2mm_wready(axi_datamover_0_M_AXI_S2MM_WREADY),
.m_axi_s2mm_wstrb(axi_datamover_0_M_AXI_S2MM_WSTRB),
.m_axi_s2mm_wvalid(axi_datamover_0_M_AXI_S2MM_WVALID),
.m_axis_mm2s_cmdsts_aclk(aclk_0_1),
.m_axis_mm2s_cmdsts_aresetn(stream_tx_ctrl_0_mm2s_resetn),
.m_axis_mm2s_sts_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
.m_axis_mm2s_sts_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
.m_axis_mm2s_sts_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
.m_axis_mm2s_sts_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
.m_axis_mm2s_sts_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID),
.m_axis_mm2s_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
.m_axis_mm2s_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
.m_axis_mm2s_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
.m_axis_mm2s_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
.m_axis_mm2s_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID),
.m_axis_s2mm_cmdsts_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.m_axis_s2mm_cmdsts_awclk(aclk_0_1),
.m_axis_s2mm_sts_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
.m_axis_s2mm_sts_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
.m_axis_s2mm_sts_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
.m_axis_s2mm_sts_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
.m_axis_s2mm_sts_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID),
.mm2s_err(axi_datamover_0_mm2s_err),
.s2mm_err(axi_datamover_0_s2mm_err),
.s_axis_mm2s_cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
.s_axis_mm2s_cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
.s_axis_mm2s_cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
.s_axis_s2mm_cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
.s_axis_s2mm_cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
.s_axis_s2mm_cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
.s_axis_s2mm_tdata(axis_data_fifo_0_M_AXIS_TDATA),
.s_axis_s2mm_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
.s_axis_s2mm_tlast(axis_data_fifo_0_M_AXIS_TLAST),
.s_axis_s2mm_tready(axis_data_fifo_0_M_AXIS_TREADY),
.s_axis_s2mm_tvalid(axis_data_fifo_0_M_AXIS_TVALID));
ssp_combo_channel_2_axil_reg_if_0_0 axil_reg_if_0
(.aclk(aclk_0_1),
.aresetn(aresetn_0_1),
.reg_rd_ack(regfile_0_reg_rd_ack),
.reg_rd_addr(axil_reg_if_0_reg_rd_addr),
.reg_rd_data(regfile_0_reg_rd_data),
.reg_rd_en(axil_reg_if_0_reg_rd_en),
.reg_rd_wait(regfile_0_reg_rd_wait),
.reg_wr_ack(regfile_0_reg_wr_ack),
.reg_wr_addr(axil_reg_if_0_reg_wr_addr),
.reg_wr_data(axil_reg_if_0_reg_wr_data),
.reg_wr_en(axil_reg_if_0_reg_wr_en),
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
.reg_wr_wait(regfile_0_reg_wr_wait),
.s_axil_araddr(s_axil_0_1_ARADDR),
.s_axil_arprot(s_axil_0_1_ARPROT),
.s_axil_arready(s_axil_0_1_ARREADY),
.s_axil_arvalid(s_axil_0_1_ARVALID),
.s_axil_awaddr(s_axil_0_1_AWADDR),
.s_axil_awprot(s_axil_0_1_AWPROT),
.s_axil_awready(s_axil_0_1_AWREADY),
.s_axil_awvalid(s_axil_0_1_AWVALID),
.s_axil_bready(s_axil_0_1_BREADY),
.s_axil_bresp(s_axil_0_1_BRESP),
.s_axil_bvalid(s_axil_0_1_BVALID),
.s_axil_rdata(s_axil_0_1_RDATA),
.s_axil_rready(s_axil_0_1_RREADY),
.s_axil_rresp(s_axil_0_1_RRESP),
.s_axil_rvalid(s_axil_0_1_RVALID),
.s_axil_wdata(s_axil_0_1_WDATA),
.s_axil_wready(s_axil_0_1_WREADY),
.s_axil_wstrb(s_axil_0_1_WSTRB),
.s_axil_wvalid(s_axil_0_1_WVALID));
ssp_combo_channel_2_axil_reg_if_1_0 axil_reg_if_1
(.aclk(aclk_0_1),
.aresetn(aresetn_0_1),
.reg_rd_ack(regfile_1_reg_rd_ack),
.reg_rd_addr(axil_reg_if_1_reg_rd_addr),
.reg_rd_data(regfile_1_reg_rd_data),
.reg_rd_en(axil_reg_if_1_reg_rd_en),
.reg_rd_wait(regfile_1_reg_rd_wait),
.reg_wr_ack(regfile_1_reg_wr_ack),
.reg_wr_addr(axil_reg_if_1_reg_wr_addr),
.reg_wr_data(axil_reg_if_1_reg_wr_data),
.reg_wr_en(axil_reg_if_1_reg_wr_en),
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
.reg_wr_wait(regfile_1_reg_wr_wait),
.s_axil_araddr(s_axil_0_2_ARADDR),
.s_axil_arprot(s_axil_0_2_ARPROT),
.s_axil_arready(s_axil_0_2_ARREADY),
.s_axil_arvalid(s_axil_0_2_ARVALID),
.s_axil_awaddr(s_axil_0_2_AWADDR),
.s_axil_awprot(s_axil_0_2_AWPROT),
.s_axil_awready(s_axil_0_2_AWREADY),
.s_axil_awvalid(s_axil_0_2_AWVALID),
.s_axil_bready(s_axil_0_2_BREADY),
.s_axil_bresp(s_axil_0_2_BRESP),
.s_axil_bvalid(s_axil_0_2_BVALID),
.s_axil_rdata(s_axil_0_2_RDATA),
.s_axil_rready(s_axil_0_2_RREADY),
.s_axil_rresp(s_axil_0_2_RRESP),
.s_axil_rvalid(s_axil_0_2_RVALID),
.s_axil_wdata(s_axil_0_2_WDATA),
.s_axil_wready(s_axil_0_2_WREADY),
.s_axil_wstrb(s_axil_0_2_WSTRB),
.s_axil_wvalid(s_axil_0_2_WVALID));
ssp_combo_channel_2_axis_data_fifo_0_0 axis_data_fifo_0
(.m_axis_tdata(axis_data_fifo_0_M_AXIS_TDATA),
.m_axis_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
.m_axis_tlast(axis_data_fifo_0_M_AXIS_TLAST),
.m_axis_tready(axis_data_fifo_0_M_AXIS_TREADY),
.m_axis_tvalid(axis_data_fifo_0_M_AXIS_TVALID),
.s_axis_aclk(aclk_0_1),
.s_axis_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.s_axis_tdata(stream_rx_ctrl_0_egress_TDATA),
.s_axis_tkeep(stream_rx_ctrl_0_egress_TKEEP),
.s_axis_tlast(stream_rx_ctrl_0_egress_TLAST),
.s_axis_tready(stream_rx_ctrl_0_egress_TREADY),
.s_axis_tstrb(stream_rx_ctrl_0_egress_TSTRB),
.s_axis_tvalid(stream_rx_ctrl_0_egress_TVALID));
ssp_combo_channel_2_axis_data_fifo_1_0 axis_data_fifo_1
(.m_axis_tdata(axis_data_fifo_1_M_AXIS_TDATA),
.m_axis_tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
.m_axis_tlast(axis_data_fifo_1_M_AXIS_TLAST),
.m_axis_tready(axis_data_fifo_1_M_AXIS_TREADY),
.m_axis_tvalid(axis_data_fifo_1_M_AXIS_TVALID),
.s_axis_aclk(aclk_0_1),
.s_axis_aresetn(aresetn_0_1),
.s_axis_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
.s_axis_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
.s_axis_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
.s_axis_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
.s_axis_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID));
ssp_combo_channel_2_blk_mem_gen_0_0 blk_mem_gen_0
(.addra(xlslice_0_Dout),
.addrb(stream_tx_ctrl_0_desc_if_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(stream_tx_ctrl_0_desc_if_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(stream_tx_ctrl_0_desc_if_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(stream_tx_ctrl_0_desc_if_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(stream_tx_ctrl_0_desc_if_WE));
ssp_combo_channel_2_regfile_0_0 regfile_0
(.clk(aclk_0_1),
.reg_0(regfile_0_reg_0),
.reg_1(regfile_0_reg_1),
.reg_2(regfile_0_reg_2),
.reg_3(regfile_0_reg_3),
.reg_4(regfile_0_reg_4),
.reg_5(regfile_0_reg_5),
.reg_6(regfile_0_reg_6),
.reg_rd_ack(regfile_0_reg_rd_ack),
.reg_rd_addr(axil_reg_if_0_reg_rd_addr[7:0]),
.reg_rd_data(regfile_0_reg_rd_data),
.reg_rd_en(axil_reg_if_0_reg_rd_en),
.reg_rd_wait(regfile_0_reg_rd_wait),
.reg_wr_ack(regfile_0_reg_wr_ack),
.reg_wr_addr(axil_reg_if_0_reg_wr_addr[7:0]),
.reg_wr_data(axil_reg_if_0_reg_wr_data),
.reg_wr_en(axil_reg_if_0_reg_wr_en),
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
.reg_wr_wait(regfile_0_reg_wr_wait),
.resetn(aresetn_0_1),
.status_0(stream_rx_ctrl_0_status_00),
.status_1(stream_rx_ctrl_0_status_01),
.status_10(ssp_rx_0_status_02),
.status_11(ssp_rx_0_status_03),
.status_12(ssp_rx_0_status_04),
.status_13(ssp_rx_0_status_05),
.status_14(ssp_rx_0_status_06),
.status_15(ssp_rx_0_status_07),
.status_2(stream_rx_ctrl_0_status_02),
.status_3(stream_rx_ctrl_0_status_03),
.status_4(stream_rx_ctrl_0_status_04),
.status_5(stream_rx_ctrl_0_status_05),
.status_6(stream_rx_ctrl_0_status_06),
.status_7(stream_rx_ctrl_0_status_07),
.status_8(ssp_rx_0_status_00),
.status_9(ssp_rx_0_status_01));
ssp_combo_channel_2_regfile_1_0 regfile_1
(.clk(aclk_0_1),
.reg_0(regfile_1_reg_0),
.reg_1(regfile_1_reg_1),
.reg_2(regfile_1_reg_2),
.reg_3(regfile_1_reg_3),
.reg_4(regfile_1_reg_4),
.reg_5(regfile_1_reg_5),
.reg_rd_ack(regfile_1_reg_rd_ack),
.reg_rd_addr(axil_reg_if_1_reg_rd_addr[7:0]),
.reg_rd_data(regfile_1_reg_rd_data),
.reg_rd_en(axil_reg_if_1_reg_rd_en),
.reg_rd_wait(regfile_1_reg_rd_wait),
.reg_wr_ack(regfile_1_reg_wr_ack),
.reg_wr_addr(axil_reg_if_1_reg_wr_addr[7:0]),
.reg_wr_data(axil_reg_if_1_reg_wr_data),
.reg_wr_en(axil_reg_if_1_reg_wr_en),
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
.reg_wr_wait(regfile_1_reg_wr_wait),
.resetn(aresetn_0_1),
.status_0(stream_tx_ctrl_0_status_00),
.status_1(stream_tx_ctrl_0_status_01),
.status_10(ssp_tx_0_status_02),
.status_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_2(stream_tx_ctrl_0_status_02),
.status_3(stream_tx_ctrl_0_status_03),
.status_4(stream_tx_ctrl_0_status_04),
.status_5(ssp_tx_0_tx_data_count),
.status_6(ssp_tx_0_tx_last_count),
.status_7(ssp_tx_0_status),
.status_8(ssp_tx_0_status_00),
.status_9(ssp_tx_0_status_01));
ssp_combo_channel_2_ssp_rx_0_0 ssp_rx_0
(.aresetn(aresetn_0_1),
.clk(aclk_0_1),
.config_00(regfile_0_reg_4),
.config_01(regfile_0_reg_5),
.config_02(regfile_0_reg_6),
.enable(stream_rx_ctrl_0_enable),
.ssp_clk(ssp_clk_0_1),
.ssp_csn(ssp_csn_0_1),
.ssp_data(ssp_data_0_1),
.status_00(ssp_rx_0_status_00),
.status_01(ssp_rx_0_status_01),
.status_02(ssp_rx_0_status_02),
.status_03(ssp_rx_0_status_03),
.status_04(ssp_rx_0_status_04),
.status_05(ssp_rx_0_status_05),
.status_06(ssp_rx_0_status_06),
.status_07(ssp_rx_0_status_07),
.tdata(ssp_rx_0_interface_axis_TDATA),
.tkeep(ssp_rx_0_interface_axis_TKEEP),
.tlast(ssp_rx_0_interface_axis_TLAST),
.tready(ssp_rx_0_interface_axis_TREADY),
.tstrb(ssp_rx_0_interface_axis_TSTRB),
.tvalid(ssp_rx_0_interface_axis_TVALID));
ssp_combo_channel_2_ssp_tx_0_0 ssp_tx_0
(.aresetn(stream_tx_ctrl_0_mm2s_resetn),
.clk(aclk_0_1),
.config_00(regfile_1_reg_4),
.config_01(regfile_1_reg_5),
.ssp_clk(ssp_tx_0_ssp_clk),
.ssp_csn(ssp_tx_0_ssp_csn),
.ssp_data(ssp_tx_0_ssp_data),
.status_00(ssp_tx_0_status_00),
.status_01(ssp_tx_0_status_01),
.status_02(ssp_tx_0_status_02),
.tdata(axis_data_fifo_1_M_AXIS_TDATA),
.tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
.tlast(axis_data_fifo_1_M_AXIS_TLAST),
.tready(axis_data_fifo_1_M_AXIS_TREADY),
.tstrb(1'b1),
.tvalid(axis_data_fifo_1_M_AXIS_TVALID));
ssp_combo_channel_2_stream_rx_ctrl_0_0 stream_rx_ctrl_0
(.clk(aclk_0_1),
.cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
.cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
.cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
.config_00(regfile_0_reg_0),
.config_01(regfile_0_reg_1),
.config_02(regfile_0_reg_2),
.config_03(regfile_0_reg_3),
.egress_tdata(stream_rx_ctrl_0_egress_TDATA),
.egress_tkeep(stream_rx_ctrl_0_egress_TKEEP),
.egress_tlast(stream_rx_ctrl_0_egress_TLAST),
.egress_tready(stream_rx_ctrl_0_egress_TREADY),
.egress_tstrb(stream_rx_ctrl_0_egress_TSTRB),
.egress_tvalid(stream_rx_ctrl_0_egress_TVALID),
.enable(stream_rx_ctrl_0_enable),
.ingress_tdata(ssp_rx_0_interface_axis_TDATA),
.ingress_tkeep(ssp_rx_0_interface_axis_TKEEP),
.ingress_tlast(ssp_rx_0_interface_axis_TLAST),
.ingress_tready(ssp_rx_0_interface_axis_TREADY),
.ingress_tstrb(ssp_rx_0_interface_axis_TSTRB),
.ingress_tvalid(ssp_rx_0_interface_axis_TVALID),
.rst_n(aresetn_0_1),
.s2mm_err(axi_datamover_0_s2mm_err),
.s2mm_resetn(stream_rx_ctrl_0_s2mm_resetn),
.status_00(stream_rx_ctrl_0_status_00),
.status_01(stream_rx_ctrl_0_status_01),
.status_02(stream_rx_ctrl_0_status_02),
.status_03(stream_rx_ctrl_0_status_03),
.status_04(stream_rx_ctrl_0_status_04),
.status_05(stream_rx_ctrl_0_status_05),
.status_06(stream_rx_ctrl_0_status_06),
.status_07(stream_rx_ctrl_0_status_07),
.status_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
.status_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
.status_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
.status_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
.status_tstrb({1'b1,1'b1,1'b1,1'b1}),
.status_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID));
ssp_combo_channel_2_stream_tx_ctrl_0_0 stream_tx_ctrl_0
(.clk(aclk_0_1),
.cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
.cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
.cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
.config_00(regfile_1_reg_0),
.config_01(regfile_1_reg_1),
.config_02(regfile_1_reg_2),
.config_03(regfile_1_reg_3),
.desc_addr(stream_tx_ctrl_0_desc_if_ADDR),
.desc_clk(stream_tx_ctrl_0_desc_if_CLK),
.desc_rdata(stream_tx_ctrl_0_desc_if_DOUT),
.desc_wdata(stream_tx_ctrl_0_desc_if_DIN),
.desc_we(stream_tx_ctrl_0_desc_if_WE),
.mm2s_err(axi_datamover_0_mm2s_err),
.mm2s_resetn(stream_tx_ctrl_0_mm2s_resetn),
.rst_n(aresetn_0_1),
.status_00(stream_tx_ctrl_0_status_00),
.status_01(stream_tx_ctrl_0_status_01),
.status_02(stream_tx_ctrl_0_status_02),
.status_03(stream_tx_ctrl_0_status_03),
.status_04(stream_tx_ctrl_0_status_04),
.status_05(ssp_tx_0_tx_data_count),
.status_06(ssp_tx_0_tx_last_count),
.status_07(ssp_tx_0_status),
.status_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
.status_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
.status_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
.status_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
.status_tstrb(1'b1),
.status_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID));
ssp_combo_channel_2_xlslice_0_0 xlslice_0
(.Din(axi_bram_ctrl_0_bram_addr_a[13:0]),
.Dout(xlslice_0_Dout));
endmodule

981
ssp_2/src/ssp_combo_channel_2.v Normal file
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@@ -0,0 +1,981 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
//Date : Tue Feb 10 16:20:32 2026
//Host : le-ThinkStation running 64-bit major release (build 9200)
//Command : generate_target ssp_combo_channel_2.bd
//Design : ssp_combo_channel_2
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "ssp_combo_channel_2,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ssp_combo_channel_2,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=14,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "ssp_combo_channel_2.hwdef" *)
module ssp_combo_channel_2
(M_AXI_MM2S_araddr,
M_AXI_MM2S_arburst,
M_AXI_MM2S_arcache,
M_AXI_MM2S_arid,
M_AXI_MM2S_arlen,
M_AXI_MM2S_arprot,
M_AXI_MM2S_arready,
M_AXI_MM2S_arsize,
M_AXI_MM2S_aruser,
M_AXI_MM2S_arvalid,
M_AXI_MM2S_rdata,
M_AXI_MM2S_rlast,
M_AXI_MM2S_rready,
M_AXI_MM2S_rresp,
M_AXI_MM2S_rvalid,
M_AXI_S2MM_awaddr,
M_AXI_S2MM_awburst,
M_AXI_S2MM_awcache,
M_AXI_S2MM_awid,
M_AXI_S2MM_awlen,
M_AXI_S2MM_awprot,
M_AXI_S2MM_awready,
M_AXI_S2MM_awsize,
M_AXI_S2MM_awuser,
M_AXI_S2MM_awvalid,
M_AXI_S2MM_bready,
M_AXI_S2MM_bresp,
M_AXI_S2MM_bvalid,
M_AXI_S2MM_wdata,
M_AXI_S2MM_wlast,
M_AXI_S2MM_wready,
M_AXI_S2MM_wstrb,
M_AXI_S2MM_wvalid,
S_AXI_TXDESC_araddr,
S_AXI_TXDESC_arburst,
S_AXI_TXDESC_arcache,
S_AXI_TXDESC_arlen,
S_AXI_TXDESC_arlock,
S_AXI_TXDESC_arprot,
S_AXI_TXDESC_arready,
S_AXI_TXDESC_arsize,
S_AXI_TXDESC_arvalid,
S_AXI_TXDESC_awaddr,
S_AXI_TXDESC_awburst,
S_AXI_TXDESC_awcache,
S_AXI_TXDESC_awlen,
S_AXI_TXDESC_awlock,
S_AXI_TXDESC_awprot,
S_AXI_TXDESC_awready,
S_AXI_TXDESC_awsize,
S_AXI_TXDESC_awvalid,
S_AXI_TXDESC_bready,
S_AXI_TXDESC_bresp,
S_AXI_TXDESC_bvalid,
S_AXI_TXDESC_rdata,
S_AXI_TXDESC_rlast,
S_AXI_TXDESC_rready,
S_AXI_TXDESC_rresp,
S_AXI_TXDESC_rvalid,
S_AXI_TXDESC_wdata,
S_AXI_TXDESC_wlast,
S_AXI_TXDESC_wready,
S_AXI_TXDESC_wstrb,
S_AXI_TXDESC_wvalid,
aresetn,
clk,
s_axil_rx_araddr,
s_axil_rx_arprot,
s_axil_rx_arready,
s_axil_rx_arvalid,
s_axil_rx_awaddr,
s_axil_rx_awprot,
s_axil_rx_awready,
s_axil_rx_awvalid,
s_axil_rx_bready,
s_axil_rx_bresp,
s_axil_rx_bvalid,
s_axil_rx_rdata,
s_axil_rx_rready,
s_axil_rx_rresp,
s_axil_rx_rvalid,
s_axil_rx_wdata,
s_axil_rx_wready,
s_axil_rx_wstrb,
s_axil_rx_wvalid,
s_axil_tx_araddr,
s_axil_tx_arprot,
s_axil_tx_arready,
s_axil_tx_arvalid,
s_axil_tx_awaddr,
s_axil_tx_awprot,
s_axil_tx_awready,
s_axil_tx_awvalid,
s_axil_tx_bready,
s_axil_tx_bresp,
s_axil_tx_bvalid,
s_axil_tx_rdata,
s_axil_tx_rready,
s_axil_tx_rresp,
s_axil_tx_rvalid,
s_axil_tx_wdata,
s_axil_tx_wready,
s_axil_tx_wstrb,
s_axil_tx_wvalid,
ssp_rx_clk,
ssp_rx_csn,
ssp_rx_data,
ssp_tx_clk,
ssp_tx_csn,
ssp_tx_data);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_MM2S, ADDR_WIDTH 32, ARUSER_WIDTH 4, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 0, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 0, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_MM2S_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST" *) output [1:0]M_AXI_MM2S_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE" *) output [3:0]M_AXI_MM2S_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID" *) output [3:0]M_AXI_MM2S_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]M_AXI_MM2S_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT" *) output [2:0]M_AXI_MM2S_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY" *) input M_AXI_MM2S_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]M_AXI_MM2S_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER" *) output [3:0]M_AXI_MM2S_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID" *) output M_AXI_MM2S_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA" *) input [127:0]M_AXI_MM2S_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST" *) input M_AXI_MM2S_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY" *) output M_AXI_MM2S_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP" *) input [1:0]M_AXI_MM2S_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID" *) input M_AXI_MM2S_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_S2MM, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 4, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 128, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 0, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE WRITE_ONLY, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]M_AXI_S2MM_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST" *) output [1:0]M_AXI_S2MM_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE" *) output [3:0]M_AXI_S2MM_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID" *) output [3:0]M_AXI_S2MM_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN" *) output [7:0]M_AXI_S2MM_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT" *) output [2:0]M_AXI_S2MM_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY" *) input M_AXI_S2MM_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE" *) output [2:0]M_AXI_S2MM_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER" *) output [3:0]M_AXI_S2MM_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID" *) output M_AXI_S2MM_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY" *) output M_AXI_S2MM_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP" *) input [1:0]M_AXI_S2MM_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID" *) input M_AXI_S2MM_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA" *) output [127:0]M_AXI_S2MM_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST" *) output M_AXI_S2MM_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY" *) input M_AXI_S2MM_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB" *) output [15:0]M_AXI_S2MM_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID" *) output M_AXI_S2MM_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_TXDESC, ADDR_WIDTH 15, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 64, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [14:0]S_AXI_TXDESC_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARBURST" *) input [1:0]S_AXI_TXDESC_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARCACHE" *) input [3:0]S_AXI_TXDESC_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLEN" *) input [7:0]S_AXI_TXDESC_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARLOCK" *) input S_AXI_TXDESC_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARPROT" *) input [2:0]S_AXI_TXDESC_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARREADY" *) output S_AXI_TXDESC_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARSIZE" *) input [2:0]S_AXI_TXDESC_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC ARVALID" *) input S_AXI_TXDESC_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWADDR" *) input [14:0]S_AXI_TXDESC_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWBURST" *) input [1:0]S_AXI_TXDESC_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWCACHE" *) input [3:0]S_AXI_TXDESC_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLEN" *) input [7:0]S_AXI_TXDESC_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWLOCK" *) input S_AXI_TXDESC_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWPROT" *) input [2:0]S_AXI_TXDESC_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWREADY" *) output S_AXI_TXDESC_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWSIZE" *) input [2:0]S_AXI_TXDESC_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC AWVALID" *) input S_AXI_TXDESC_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BREADY" *) input S_AXI_TXDESC_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BRESP" *) output [1:0]S_AXI_TXDESC_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC BVALID" *) output S_AXI_TXDESC_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RDATA" *) output [63:0]S_AXI_TXDESC_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RLAST" *) output S_AXI_TXDESC_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RREADY" *) input S_AXI_TXDESC_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RRESP" *) output [1:0]S_AXI_TXDESC_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC RVALID" *) output S_AXI_TXDESC_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WDATA" *) input [63:0]S_AXI_TXDESC_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WLAST" *) input S_AXI_TXDESC_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WREADY" *) output S_AXI_TXDESC_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WSTRB" *) input [7:0]S_AXI_TXDESC_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_TXDESC WVALID" *) input S_AXI_TXDESC_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M_AXI_MM2S:M_AXI_S2MM:S_AXI_TXDESC:s_axil_rx:s_axil_tx, ASSOCIATED_RESET aresetn, CLK_DOMAIN ssp_combo_channel_2_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_rx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_rx_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARPROT" *) input [2:0]s_axil_rx_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARREADY" *) output s_axil_rx_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx ARVALID" *) input s_axil_rx_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWADDR" *) input [31:0]s_axil_rx_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWPROT" *) input [2:0]s_axil_rx_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWREADY" *) output s_axil_rx_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx AWVALID" *) input s_axil_rx_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BREADY" *) input s_axil_rx_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BRESP" *) output [1:0]s_axil_rx_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx BVALID" *) output s_axil_rx_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RDATA" *) output [31:0]s_axil_rx_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RREADY" *) input s_axil_rx_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RRESP" *) output [1:0]s_axil_rx_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx RVALID" *) output s_axil_rx_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WDATA" *) input [31:0]s_axil_rx_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WREADY" *) output s_axil_rx_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WSTRB" *) input [3:0]s_axil_rx_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_rx WVALID" *) input s_axil_rx_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axil_tx, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN ssp_combo_channel_2_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [31:0]s_axil_tx_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARPROT" *) input [2:0]s_axil_tx_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARREADY" *) output s_axil_tx_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx ARVALID" *) input s_axil_tx_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWADDR" *) input [31:0]s_axil_tx_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWPROT" *) input [2:0]s_axil_tx_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWREADY" *) output s_axil_tx_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx AWVALID" *) input s_axil_tx_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BREADY" *) input s_axil_tx_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BRESP" *) output [1:0]s_axil_tx_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx BVALID" *) output s_axil_tx_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RDATA" *) output [31:0]s_axil_tx_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RREADY" *) input s_axil_tx_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RRESP" *) output [1:0]s_axil_tx_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx RVALID" *) output s_axil_tx_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WDATA" *) input [31:0]s_axil_tx_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WREADY" *) output s_axil_tx_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WSTRB" *) input [3:0]s_axil_tx_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axil_tx WVALID" *) input s_axil_tx_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_RX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_RX_CLK, CLK_DOMAIN ssp_combo_channel_2_ssp_rx_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input ssp_rx_clk;
input ssp_rx_csn;
input ssp_rx_data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SSP_TX_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SSP_TX_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) output ssp_tx_clk;
output ssp_tx_csn;
output ssp_tx_data;
wire [14:0]S_AXI_0_1_ARADDR;
wire [1:0]S_AXI_0_1_ARBURST;
wire [3:0]S_AXI_0_1_ARCACHE;
wire [7:0]S_AXI_0_1_ARLEN;
wire S_AXI_0_1_ARLOCK;
wire [2:0]S_AXI_0_1_ARPROT;
wire S_AXI_0_1_ARREADY;
wire [2:0]S_AXI_0_1_ARSIZE;
wire S_AXI_0_1_ARVALID;
wire [14:0]S_AXI_0_1_AWADDR;
wire [1:0]S_AXI_0_1_AWBURST;
wire [3:0]S_AXI_0_1_AWCACHE;
wire [7:0]S_AXI_0_1_AWLEN;
wire S_AXI_0_1_AWLOCK;
wire [2:0]S_AXI_0_1_AWPROT;
wire S_AXI_0_1_AWREADY;
wire [2:0]S_AXI_0_1_AWSIZE;
wire S_AXI_0_1_AWVALID;
wire S_AXI_0_1_BREADY;
wire [1:0]S_AXI_0_1_BRESP;
wire S_AXI_0_1_BVALID;
wire [63:0]S_AXI_0_1_RDATA;
wire S_AXI_0_1_RLAST;
wire S_AXI_0_1_RREADY;
wire [1:0]S_AXI_0_1_RRESP;
wire S_AXI_0_1_RVALID;
wire [63:0]S_AXI_0_1_WDATA;
wire S_AXI_0_1_WLAST;
wire S_AXI_0_1_WREADY;
wire [7:0]S_AXI_0_1_WSTRB;
wire S_AXI_0_1_WVALID;
wire aclk_0_1;
wire aresetn_0_1;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire [7:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [14:0]axi_bram_ctrl_0_bram_addr_a;
wire [7:0]axi_datamover_0_M_AXIS_MM2S_STS_TDATA;
wire [0:0]axi_datamover_0_M_AXIS_MM2S_STS_TKEEP;
wire axi_datamover_0_M_AXIS_MM2S_STS_TLAST;
wire axi_datamover_0_M_AXIS_MM2S_STS_TREADY;
wire axi_datamover_0_M_AXIS_MM2S_STS_TVALID;
wire [7:0]axi_datamover_0_M_AXIS_MM2S_TDATA;
wire [0:0]axi_datamover_0_M_AXIS_MM2S_TKEEP;
wire axi_datamover_0_M_AXIS_MM2S_TLAST;
wire axi_datamover_0_M_AXIS_MM2S_TREADY;
wire axi_datamover_0_M_AXIS_MM2S_TVALID;
wire [31:0]axi_datamover_0_M_AXIS_S2MM_STS_TDATA;
wire [3:0]axi_datamover_0_M_AXIS_S2MM_STS_TKEEP;
wire axi_datamover_0_M_AXIS_S2MM_STS_TLAST;
wire axi_datamover_0_M_AXIS_S2MM_STS_TREADY;
wire axi_datamover_0_M_AXIS_S2MM_STS_TVALID;
wire [31:0]axi_datamover_0_M_AXI_MM2S_ARADDR;
wire [1:0]axi_datamover_0_M_AXI_MM2S_ARBURST;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARCACHE;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARID;
wire [7:0]axi_datamover_0_M_AXI_MM2S_ARLEN;
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARPROT;
wire axi_datamover_0_M_AXI_MM2S_ARREADY;
wire [2:0]axi_datamover_0_M_AXI_MM2S_ARSIZE;
wire [3:0]axi_datamover_0_M_AXI_MM2S_ARUSER;
wire axi_datamover_0_M_AXI_MM2S_ARVALID;
wire [127:0]axi_datamover_0_M_AXI_MM2S_RDATA;
wire axi_datamover_0_M_AXI_MM2S_RLAST;
wire axi_datamover_0_M_AXI_MM2S_RREADY;
wire [1:0]axi_datamover_0_M_AXI_MM2S_RRESP;
wire axi_datamover_0_M_AXI_MM2S_RVALID;
wire [31:0]axi_datamover_0_M_AXI_S2MM_AWADDR;
wire [1:0]axi_datamover_0_M_AXI_S2MM_AWBURST;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWCACHE;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWID;
wire [7:0]axi_datamover_0_M_AXI_S2MM_AWLEN;
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWPROT;
wire axi_datamover_0_M_AXI_S2MM_AWREADY;
wire [2:0]axi_datamover_0_M_AXI_S2MM_AWSIZE;
wire [3:0]axi_datamover_0_M_AXI_S2MM_AWUSER;
wire axi_datamover_0_M_AXI_S2MM_AWVALID;
wire axi_datamover_0_M_AXI_S2MM_BREADY;
wire [1:0]axi_datamover_0_M_AXI_S2MM_BRESP;
wire axi_datamover_0_M_AXI_S2MM_BVALID;
wire [127:0]axi_datamover_0_M_AXI_S2MM_WDATA;
wire axi_datamover_0_M_AXI_S2MM_WLAST;
wire axi_datamover_0_M_AXI_S2MM_WREADY;
wire [15:0]axi_datamover_0_M_AXI_S2MM_WSTRB;
wire axi_datamover_0_M_AXI_S2MM_WVALID;
wire axi_datamover_0_mm2s_err;
wire axi_datamover_0_s2mm_err;
wire [31:0]axil_reg_if_0_reg_rd_addr;
wire axil_reg_if_0_reg_rd_en;
wire [31:0]axil_reg_if_0_reg_wr_addr;
wire [31:0]axil_reg_if_0_reg_wr_data;
wire axil_reg_if_0_reg_wr_en;
wire [3:0]axil_reg_if_0_reg_wr_strb;
wire [31:0]axil_reg_if_1_reg_rd_addr;
wire axil_reg_if_1_reg_rd_en;
wire [31:0]axil_reg_if_1_reg_wr_addr;
wire [31:0]axil_reg_if_1_reg_wr_data;
wire axil_reg_if_1_reg_wr_en;
wire [3:0]axil_reg_if_1_reg_wr_strb;
wire [7:0]axis_data_fifo_0_M_AXIS_TDATA;
wire [0:0]axis_data_fifo_0_M_AXIS_TKEEP;
wire axis_data_fifo_0_M_AXIS_TLAST;
wire axis_data_fifo_0_M_AXIS_TREADY;
wire axis_data_fifo_0_M_AXIS_TVALID;
wire [7:0]axis_data_fifo_1_M_AXIS_TDATA;
wire [0:0]axis_data_fifo_1_M_AXIS_TKEEP;
wire axis_data_fifo_1_M_AXIS_TLAST;
wire axis_data_fifo_1_M_AXIS_TREADY;
wire axis_data_fifo_1_M_AXIS_TVALID;
wire [31:0]regfile_0_reg_0;
wire [31:0]regfile_0_reg_1;
wire [31:0]regfile_0_reg_2;
wire [31:0]regfile_0_reg_3;
wire [31:0]regfile_0_reg_4;
wire [31:0]regfile_0_reg_5;
wire [31:0]regfile_0_reg_6;
wire regfile_0_reg_rd_ack;
wire [31:0]regfile_0_reg_rd_data;
wire regfile_0_reg_rd_wait;
wire regfile_0_reg_wr_ack;
wire regfile_0_reg_wr_wait;
wire [31:0]regfile_1_reg_0;
wire [31:0]regfile_1_reg_1;
wire [31:0]regfile_1_reg_2;
wire [31:0]regfile_1_reg_3;
wire [31:0]regfile_1_reg_4;
wire [31:0]regfile_1_reg_5;
wire regfile_1_reg_rd_ack;
wire [31:0]regfile_1_reg_rd_data;
wire regfile_1_reg_rd_wait;
wire regfile_1_reg_wr_ack;
wire regfile_1_reg_wr_wait;
wire [31:0]s_axil_0_1_ARADDR;
wire [2:0]s_axil_0_1_ARPROT;
wire s_axil_0_1_ARREADY;
wire s_axil_0_1_ARVALID;
wire [31:0]s_axil_0_1_AWADDR;
wire [2:0]s_axil_0_1_AWPROT;
wire s_axil_0_1_AWREADY;
wire s_axil_0_1_AWVALID;
wire s_axil_0_1_BREADY;
wire [1:0]s_axil_0_1_BRESP;
wire s_axil_0_1_BVALID;
wire [31:0]s_axil_0_1_RDATA;
wire s_axil_0_1_RREADY;
wire [1:0]s_axil_0_1_RRESP;
wire s_axil_0_1_RVALID;
wire [31:0]s_axil_0_1_WDATA;
wire s_axil_0_1_WREADY;
wire [3:0]s_axil_0_1_WSTRB;
wire s_axil_0_1_WVALID;
wire [31:0]s_axil_0_2_ARADDR;
wire [2:0]s_axil_0_2_ARPROT;
wire s_axil_0_2_ARREADY;
wire s_axil_0_2_ARVALID;
wire [31:0]s_axil_0_2_AWADDR;
wire [2:0]s_axil_0_2_AWPROT;
wire s_axil_0_2_AWREADY;
wire s_axil_0_2_AWVALID;
wire s_axil_0_2_BREADY;
wire [1:0]s_axil_0_2_BRESP;
wire s_axil_0_2_BVALID;
wire [31:0]s_axil_0_2_RDATA;
wire s_axil_0_2_RREADY;
wire [1:0]s_axil_0_2_RRESP;
wire s_axil_0_2_RVALID;
wire [31:0]s_axil_0_2_WDATA;
wire s_axil_0_2_WREADY;
wire [3:0]s_axil_0_2_WSTRB;
wire s_axil_0_2_WVALID;
wire ssp_clk_0_1;
wire ssp_csn_0_1;
wire ssp_data_0_1;
wire [7:0]ssp_rx_0_interface_axis_TDATA;
wire ssp_rx_0_interface_axis_TKEEP;
wire ssp_rx_0_interface_axis_TLAST;
wire ssp_rx_0_interface_axis_TREADY;
wire ssp_rx_0_interface_axis_TSTRB;
wire ssp_rx_0_interface_axis_TVALID;
wire [31:0]ssp_rx_0_status_00;
wire [31:0]ssp_rx_0_status_01;
wire [31:0]ssp_rx_0_status_02;
wire [31:0]ssp_rx_0_status_03;
wire [31:0]ssp_rx_0_status_04;
wire [31:0]ssp_rx_0_status_05;
wire [31:0]ssp_rx_0_status_06;
wire [31:0]ssp_rx_0_status_07;
wire ssp_tx_0_ssp_clk;
wire ssp_tx_0_ssp_csn;
wire ssp_tx_0_ssp_data;
wire [31:0]ssp_tx_0_status;
wire [31:0]ssp_tx_0_status_00;
wire [31:0]ssp_tx_0_status_01;
wire [31:0]ssp_tx_0_status_02;
wire [31:0]ssp_tx_0_tx_data_count;
wire [31:0]ssp_tx_0_tx_last_count;
wire [71:0]stream_rx_ctrl_0_cmd_TDATA;
wire stream_rx_ctrl_0_cmd_TREADY;
wire stream_rx_ctrl_0_cmd_TVALID;
wire [7:0]stream_rx_ctrl_0_egress_TDATA;
wire [0:0]stream_rx_ctrl_0_egress_TKEEP;
wire stream_rx_ctrl_0_egress_TLAST;
wire stream_rx_ctrl_0_egress_TREADY;
wire [0:0]stream_rx_ctrl_0_egress_TSTRB;
wire stream_rx_ctrl_0_egress_TVALID;
wire stream_rx_ctrl_0_enable;
wire stream_rx_ctrl_0_s2mm_resetn;
wire [31:0]stream_rx_ctrl_0_status_00;
wire [31:0]stream_rx_ctrl_0_status_01;
wire [31:0]stream_rx_ctrl_0_status_02;
wire [31:0]stream_rx_ctrl_0_status_03;
wire [31:0]stream_rx_ctrl_0_status_04;
wire [31:0]stream_rx_ctrl_0_status_05;
wire [31:0]stream_rx_ctrl_0_status_06;
wire [31:0]stream_rx_ctrl_0_status_07;
wire [71:0]stream_tx_ctrl_0_cmd_TDATA;
wire stream_tx_ctrl_0_cmd_TREADY;
wire stream_tx_ctrl_0_cmd_TVALID;
wire [10:0]stream_tx_ctrl_0_desc_if_ADDR;
wire stream_tx_ctrl_0_desc_if_CLK;
wire [63:0]stream_tx_ctrl_0_desc_if_DIN;
wire [63:0]stream_tx_ctrl_0_desc_if_DOUT;
wire [7:0]stream_tx_ctrl_0_desc_if_WE;
wire stream_tx_ctrl_0_mm2s_resetn;
wire [31:0]stream_tx_ctrl_0_status_00;
wire [31:0]stream_tx_ctrl_0_status_01;
wire [31:0]stream_tx_ctrl_0_status_02;
wire [31:0]stream_tx_ctrl_0_status_03;
wire [31:0]stream_tx_ctrl_0_status_04;
wire [10:0]xlslice_0_Dout;
assign M_AXI_MM2S_araddr[31:0] = axi_datamover_0_M_AXI_MM2S_ARADDR;
assign M_AXI_MM2S_arburst[1:0] = axi_datamover_0_M_AXI_MM2S_ARBURST;
assign M_AXI_MM2S_arcache[3:0] = axi_datamover_0_M_AXI_MM2S_ARCACHE;
assign M_AXI_MM2S_arid[3:0] = axi_datamover_0_M_AXI_MM2S_ARID;
assign M_AXI_MM2S_arlen[7:0] = axi_datamover_0_M_AXI_MM2S_ARLEN;
assign M_AXI_MM2S_arprot[2:0] = axi_datamover_0_M_AXI_MM2S_ARPROT;
assign M_AXI_MM2S_arsize[2:0] = axi_datamover_0_M_AXI_MM2S_ARSIZE;
assign M_AXI_MM2S_aruser[3:0] = axi_datamover_0_M_AXI_MM2S_ARUSER;
assign M_AXI_MM2S_arvalid = axi_datamover_0_M_AXI_MM2S_ARVALID;
assign M_AXI_MM2S_rready = axi_datamover_0_M_AXI_MM2S_RREADY;
assign M_AXI_S2MM_awaddr[31:0] = axi_datamover_0_M_AXI_S2MM_AWADDR;
assign M_AXI_S2MM_awburst[1:0] = axi_datamover_0_M_AXI_S2MM_AWBURST;
assign M_AXI_S2MM_awcache[3:0] = axi_datamover_0_M_AXI_S2MM_AWCACHE;
assign M_AXI_S2MM_awid[3:0] = axi_datamover_0_M_AXI_S2MM_AWID;
assign M_AXI_S2MM_awlen[7:0] = axi_datamover_0_M_AXI_S2MM_AWLEN;
assign M_AXI_S2MM_awprot[2:0] = axi_datamover_0_M_AXI_S2MM_AWPROT;
assign M_AXI_S2MM_awsize[2:0] = axi_datamover_0_M_AXI_S2MM_AWSIZE;
assign M_AXI_S2MM_awuser[3:0] = axi_datamover_0_M_AXI_S2MM_AWUSER;
assign M_AXI_S2MM_awvalid = axi_datamover_0_M_AXI_S2MM_AWVALID;
assign M_AXI_S2MM_bready = axi_datamover_0_M_AXI_S2MM_BREADY;
assign M_AXI_S2MM_wdata[127:0] = axi_datamover_0_M_AXI_S2MM_WDATA;
assign M_AXI_S2MM_wlast = axi_datamover_0_M_AXI_S2MM_WLAST;
assign M_AXI_S2MM_wstrb[15:0] = axi_datamover_0_M_AXI_S2MM_WSTRB;
assign M_AXI_S2MM_wvalid = axi_datamover_0_M_AXI_S2MM_WVALID;
assign S_AXI_0_1_ARADDR = S_AXI_TXDESC_araddr[14:0];
assign S_AXI_0_1_ARBURST = S_AXI_TXDESC_arburst[1:0];
assign S_AXI_0_1_ARCACHE = S_AXI_TXDESC_arcache[3:0];
assign S_AXI_0_1_ARLEN = S_AXI_TXDESC_arlen[7:0];
assign S_AXI_0_1_ARLOCK = S_AXI_TXDESC_arlock;
assign S_AXI_0_1_ARPROT = S_AXI_TXDESC_arprot[2:0];
assign S_AXI_0_1_ARSIZE = S_AXI_TXDESC_arsize[2:0];
assign S_AXI_0_1_ARVALID = S_AXI_TXDESC_arvalid;
assign S_AXI_0_1_AWADDR = S_AXI_TXDESC_awaddr[14:0];
assign S_AXI_0_1_AWBURST = S_AXI_TXDESC_awburst[1:0];
assign S_AXI_0_1_AWCACHE = S_AXI_TXDESC_awcache[3:0];
assign S_AXI_0_1_AWLEN = S_AXI_TXDESC_awlen[7:0];
assign S_AXI_0_1_AWLOCK = S_AXI_TXDESC_awlock;
assign S_AXI_0_1_AWPROT = S_AXI_TXDESC_awprot[2:0];
assign S_AXI_0_1_AWSIZE = S_AXI_TXDESC_awsize[2:0];
assign S_AXI_0_1_AWVALID = S_AXI_TXDESC_awvalid;
assign S_AXI_0_1_BREADY = S_AXI_TXDESC_bready;
assign S_AXI_0_1_RREADY = S_AXI_TXDESC_rready;
assign S_AXI_0_1_WDATA = S_AXI_TXDESC_wdata[63:0];
assign S_AXI_0_1_WLAST = S_AXI_TXDESC_wlast;
assign S_AXI_0_1_WSTRB = S_AXI_TXDESC_wstrb[7:0];
assign S_AXI_0_1_WVALID = S_AXI_TXDESC_wvalid;
assign S_AXI_TXDESC_arready = S_AXI_0_1_ARREADY;
assign S_AXI_TXDESC_awready = S_AXI_0_1_AWREADY;
assign S_AXI_TXDESC_bresp[1:0] = S_AXI_0_1_BRESP;
assign S_AXI_TXDESC_bvalid = S_AXI_0_1_BVALID;
assign S_AXI_TXDESC_rdata[63:0] = S_AXI_0_1_RDATA;
assign S_AXI_TXDESC_rlast = S_AXI_0_1_RLAST;
assign S_AXI_TXDESC_rresp[1:0] = S_AXI_0_1_RRESP;
assign S_AXI_TXDESC_rvalid = S_AXI_0_1_RVALID;
assign S_AXI_TXDESC_wready = S_AXI_0_1_WREADY;
assign aclk_0_1 = clk;
assign aresetn_0_1 = aresetn;
assign axi_datamover_0_M_AXI_MM2S_ARREADY = M_AXI_MM2S_arready;
assign axi_datamover_0_M_AXI_MM2S_RDATA = M_AXI_MM2S_rdata[127:0];
assign axi_datamover_0_M_AXI_MM2S_RLAST = M_AXI_MM2S_rlast;
assign axi_datamover_0_M_AXI_MM2S_RRESP = M_AXI_MM2S_rresp[1:0];
assign axi_datamover_0_M_AXI_MM2S_RVALID = M_AXI_MM2S_rvalid;
assign axi_datamover_0_M_AXI_S2MM_AWREADY = M_AXI_S2MM_awready;
assign axi_datamover_0_M_AXI_S2MM_BRESP = M_AXI_S2MM_bresp[1:0];
assign axi_datamover_0_M_AXI_S2MM_BVALID = M_AXI_S2MM_bvalid;
assign axi_datamover_0_M_AXI_S2MM_WREADY = M_AXI_S2MM_wready;
assign s_axil_0_1_ARADDR = s_axil_rx_araddr[31:0];
assign s_axil_0_1_ARPROT = s_axil_rx_arprot[2:0];
assign s_axil_0_1_ARVALID = s_axil_rx_arvalid;
assign s_axil_0_1_AWADDR = s_axil_rx_awaddr[31:0];
assign s_axil_0_1_AWPROT = s_axil_rx_awprot[2:0];
assign s_axil_0_1_AWVALID = s_axil_rx_awvalid;
assign s_axil_0_1_BREADY = s_axil_rx_bready;
assign s_axil_0_1_RREADY = s_axil_rx_rready;
assign s_axil_0_1_WDATA = s_axil_rx_wdata[31:0];
assign s_axil_0_1_WSTRB = s_axil_rx_wstrb[3:0];
assign s_axil_0_1_WVALID = s_axil_rx_wvalid;
assign s_axil_0_2_ARADDR = s_axil_tx_araddr[31:0];
assign s_axil_0_2_ARPROT = s_axil_tx_arprot[2:0];
assign s_axil_0_2_ARVALID = s_axil_tx_arvalid;
assign s_axil_0_2_AWADDR = s_axil_tx_awaddr[31:0];
assign s_axil_0_2_AWPROT = s_axil_tx_awprot[2:0];
assign s_axil_0_2_AWVALID = s_axil_tx_awvalid;
assign s_axil_0_2_BREADY = s_axil_tx_bready;
assign s_axil_0_2_RREADY = s_axil_tx_rready;
assign s_axil_0_2_WDATA = s_axil_tx_wdata[31:0];
assign s_axil_0_2_WSTRB = s_axil_tx_wstrb[3:0];
assign s_axil_0_2_WVALID = s_axil_tx_wvalid;
assign s_axil_rx_arready = s_axil_0_1_ARREADY;
assign s_axil_rx_awready = s_axil_0_1_AWREADY;
assign s_axil_rx_bresp[1:0] = s_axil_0_1_BRESP;
assign s_axil_rx_bvalid = s_axil_0_1_BVALID;
assign s_axil_rx_rdata[31:0] = s_axil_0_1_RDATA;
assign s_axil_rx_rresp[1:0] = s_axil_0_1_RRESP;
assign s_axil_rx_rvalid = s_axil_0_1_RVALID;
assign s_axil_rx_wready = s_axil_0_1_WREADY;
assign s_axil_tx_arready = s_axil_0_2_ARREADY;
assign s_axil_tx_awready = s_axil_0_2_AWREADY;
assign s_axil_tx_bresp[1:0] = s_axil_0_2_BRESP;
assign s_axil_tx_bvalid = s_axil_0_2_BVALID;
assign s_axil_tx_rdata[31:0] = s_axil_0_2_RDATA;
assign s_axil_tx_rresp[1:0] = s_axil_0_2_RRESP;
assign s_axil_tx_rvalid = s_axil_0_2_RVALID;
assign s_axil_tx_wready = s_axil_0_2_WREADY;
assign ssp_clk_0_1 = ssp_rx_clk;
assign ssp_csn_0_1 = ssp_rx_csn;
assign ssp_data_0_1 = ssp_rx_data;
assign ssp_tx_clk = ssp_tx_0_ssp_clk;
assign ssp_tx_csn = ssp_tx_0_ssp_csn;
assign ssp_tx_data = ssp_tx_0_ssp_data;
ssp_combo_channel_2_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_bram_addr_a),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(aclk_0_1),
.s_axi_araddr(S_AXI_0_1_ARADDR),
.s_axi_arburst(S_AXI_0_1_ARBURST),
.s_axi_arcache(S_AXI_0_1_ARCACHE),
.s_axi_aresetn(aresetn_0_1),
.s_axi_arlen(S_AXI_0_1_ARLEN),
.s_axi_arlock(S_AXI_0_1_ARLOCK),
.s_axi_arprot(S_AXI_0_1_ARPROT),
.s_axi_arready(S_AXI_0_1_ARREADY),
.s_axi_arsize(S_AXI_0_1_ARSIZE),
.s_axi_arvalid(S_AXI_0_1_ARVALID),
.s_axi_awaddr(S_AXI_0_1_AWADDR),
.s_axi_awburst(S_AXI_0_1_AWBURST),
.s_axi_awcache(S_AXI_0_1_AWCACHE),
.s_axi_awlen(S_AXI_0_1_AWLEN),
.s_axi_awlock(S_AXI_0_1_AWLOCK),
.s_axi_awprot(S_AXI_0_1_AWPROT),
.s_axi_awready(S_AXI_0_1_AWREADY),
.s_axi_awsize(S_AXI_0_1_AWSIZE),
.s_axi_awvalid(S_AXI_0_1_AWVALID),
.s_axi_bready(S_AXI_0_1_BREADY),
.s_axi_bresp(S_AXI_0_1_BRESP),
.s_axi_bvalid(S_AXI_0_1_BVALID),
.s_axi_rdata(S_AXI_0_1_RDATA),
.s_axi_rlast(S_AXI_0_1_RLAST),
.s_axi_rready(S_AXI_0_1_RREADY),
.s_axi_rresp(S_AXI_0_1_RRESP),
.s_axi_rvalid(S_AXI_0_1_RVALID),
.s_axi_wdata(S_AXI_0_1_WDATA),
.s_axi_wlast(S_AXI_0_1_WLAST),
.s_axi_wready(S_AXI_0_1_WREADY),
.s_axi_wstrb(S_AXI_0_1_WSTRB),
.s_axi_wvalid(S_AXI_0_1_WVALID));
ssp_combo_channel_2_axi_datamover_0_0 axi_datamover_0
(.m_axi_mm2s_aclk(aclk_0_1),
.m_axi_mm2s_araddr(axi_datamover_0_M_AXI_MM2S_ARADDR),
.m_axi_mm2s_arburst(axi_datamover_0_M_AXI_MM2S_ARBURST),
.m_axi_mm2s_arcache(axi_datamover_0_M_AXI_MM2S_ARCACHE),
.m_axi_mm2s_aresetn(stream_tx_ctrl_0_mm2s_resetn),
.m_axi_mm2s_arid(axi_datamover_0_M_AXI_MM2S_ARID),
.m_axi_mm2s_arlen(axi_datamover_0_M_AXI_MM2S_ARLEN),
.m_axi_mm2s_arprot(axi_datamover_0_M_AXI_MM2S_ARPROT),
.m_axi_mm2s_arready(axi_datamover_0_M_AXI_MM2S_ARREADY),
.m_axi_mm2s_arsize(axi_datamover_0_M_AXI_MM2S_ARSIZE),
.m_axi_mm2s_aruser(axi_datamover_0_M_AXI_MM2S_ARUSER),
.m_axi_mm2s_arvalid(axi_datamover_0_M_AXI_MM2S_ARVALID),
.m_axi_mm2s_rdata(axi_datamover_0_M_AXI_MM2S_RDATA),
.m_axi_mm2s_rlast(axi_datamover_0_M_AXI_MM2S_RLAST),
.m_axi_mm2s_rready(axi_datamover_0_M_AXI_MM2S_RREADY),
.m_axi_mm2s_rresp(axi_datamover_0_M_AXI_MM2S_RRESP),
.m_axi_mm2s_rvalid(axi_datamover_0_M_AXI_MM2S_RVALID),
.m_axi_s2mm_aclk(aclk_0_1),
.m_axi_s2mm_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.m_axi_s2mm_awaddr(axi_datamover_0_M_AXI_S2MM_AWADDR),
.m_axi_s2mm_awburst(axi_datamover_0_M_AXI_S2MM_AWBURST),
.m_axi_s2mm_awcache(axi_datamover_0_M_AXI_S2MM_AWCACHE),
.m_axi_s2mm_awid(axi_datamover_0_M_AXI_S2MM_AWID),
.m_axi_s2mm_awlen(axi_datamover_0_M_AXI_S2MM_AWLEN),
.m_axi_s2mm_awprot(axi_datamover_0_M_AXI_S2MM_AWPROT),
.m_axi_s2mm_awready(axi_datamover_0_M_AXI_S2MM_AWREADY),
.m_axi_s2mm_awsize(axi_datamover_0_M_AXI_S2MM_AWSIZE),
.m_axi_s2mm_awuser(axi_datamover_0_M_AXI_S2MM_AWUSER),
.m_axi_s2mm_awvalid(axi_datamover_0_M_AXI_S2MM_AWVALID),
.m_axi_s2mm_bready(axi_datamover_0_M_AXI_S2MM_BREADY),
.m_axi_s2mm_bresp(axi_datamover_0_M_AXI_S2MM_BRESP),
.m_axi_s2mm_bvalid(axi_datamover_0_M_AXI_S2MM_BVALID),
.m_axi_s2mm_wdata(axi_datamover_0_M_AXI_S2MM_WDATA),
.m_axi_s2mm_wlast(axi_datamover_0_M_AXI_S2MM_WLAST),
.m_axi_s2mm_wready(axi_datamover_0_M_AXI_S2MM_WREADY),
.m_axi_s2mm_wstrb(axi_datamover_0_M_AXI_S2MM_WSTRB),
.m_axi_s2mm_wvalid(axi_datamover_0_M_AXI_S2MM_WVALID),
.m_axis_mm2s_cmdsts_aclk(aclk_0_1),
.m_axis_mm2s_cmdsts_aresetn(stream_tx_ctrl_0_mm2s_resetn),
.m_axis_mm2s_sts_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
.m_axis_mm2s_sts_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
.m_axis_mm2s_sts_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
.m_axis_mm2s_sts_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
.m_axis_mm2s_sts_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID),
.m_axis_mm2s_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
.m_axis_mm2s_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
.m_axis_mm2s_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
.m_axis_mm2s_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
.m_axis_mm2s_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID),
.m_axis_s2mm_cmdsts_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.m_axis_s2mm_cmdsts_awclk(aclk_0_1),
.m_axis_s2mm_sts_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
.m_axis_s2mm_sts_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
.m_axis_s2mm_sts_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
.m_axis_s2mm_sts_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
.m_axis_s2mm_sts_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID),
.mm2s_err(axi_datamover_0_mm2s_err),
.s2mm_err(axi_datamover_0_s2mm_err),
.s_axis_mm2s_cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
.s_axis_mm2s_cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
.s_axis_mm2s_cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
.s_axis_s2mm_cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
.s_axis_s2mm_cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
.s_axis_s2mm_cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
.s_axis_s2mm_tdata(axis_data_fifo_0_M_AXIS_TDATA),
.s_axis_s2mm_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
.s_axis_s2mm_tlast(axis_data_fifo_0_M_AXIS_TLAST),
.s_axis_s2mm_tready(axis_data_fifo_0_M_AXIS_TREADY),
.s_axis_s2mm_tvalid(axis_data_fifo_0_M_AXIS_TVALID));
ssp_combo_channel_2_axil_reg_if_0_0 axil_reg_if_0
(.aclk(aclk_0_1),
.aresetn(aresetn_0_1),
.reg_rd_ack(regfile_0_reg_rd_ack),
.reg_rd_addr(axil_reg_if_0_reg_rd_addr),
.reg_rd_data(regfile_0_reg_rd_data),
.reg_rd_en(axil_reg_if_0_reg_rd_en),
.reg_rd_wait(regfile_0_reg_rd_wait),
.reg_wr_ack(regfile_0_reg_wr_ack),
.reg_wr_addr(axil_reg_if_0_reg_wr_addr),
.reg_wr_data(axil_reg_if_0_reg_wr_data),
.reg_wr_en(axil_reg_if_0_reg_wr_en),
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
.reg_wr_wait(regfile_0_reg_wr_wait),
.s_axil_araddr(s_axil_0_1_ARADDR),
.s_axil_arprot(s_axil_0_1_ARPROT),
.s_axil_arready(s_axil_0_1_ARREADY),
.s_axil_arvalid(s_axil_0_1_ARVALID),
.s_axil_awaddr(s_axil_0_1_AWADDR),
.s_axil_awprot(s_axil_0_1_AWPROT),
.s_axil_awready(s_axil_0_1_AWREADY),
.s_axil_awvalid(s_axil_0_1_AWVALID),
.s_axil_bready(s_axil_0_1_BREADY),
.s_axil_bresp(s_axil_0_1_BRESP),
.s_axil_bvalid(s_axil_0_1_BVALID),
.s_axil_rdata(s_axil_0_1_RDATA),
.s_axil_rready(s_axil_0_1_RREADY),
.s_axil_rresp(s_axil_0_1_RRESP),
.s_axil_rvalid(s_axil_0_1_RVALID),
.s_axil_wdata(s_axil_0_1_WDATA),
.s_axil_wready(s_axil_0_1_WREADY),
.s_axil_wstrb(s_axil_0_1_WSTRB),
.s_axil_wvalid(s_axil_0_1_WVALID));
ssp_combo_channel_2_axil_reg_if_1_0 axil_reg_if_1
(.aclk(aclk_0_1),
.aresetn(aresetn_0_1),
.reg_rd_ack(regfile_1_reg_rd_ack),
.reg_rd_addr(axil_reg_if_1_reg_rd_addr),
.reg_rd_data(regfile_1_reg_rd_data),
.reg_rd_en(axil_reg_if_1_reg_rd_en),
.reg_rd_wait(regfile_1_reg_rd_wait),
.reg_wr_ack(regfile_1_reg_wr_ack),
.reg_wr_addr(axil_reg_if_1_reg_wr_addr),
.reg_wr_data(axil_reg_if_1_reg_wr_data),
.reg_wr_en(axil_reg_if_1_reg_wr_en),
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
.reg_wr_wait(regfile_1_reg_wr_wait),
.s_axil_araddr(s_axil_0_2_ARADDR),
.s_axil_arprot(s_axil_0_2_ARPROT),
.s_axil_arready(s_axil_0_2_ARREADY),
.s_axil_arvalid(s_axil_0_2_ARVALID),
.s_axil_awaddr(s_axil_0_2_AWADDR),
.s_axil_awprot(s_axil_0_2_AWPROT),
.s_axil_awready(s_axil_0_2_AWREADY),
.s_axil_awvalid(s_axil_0_2_AWVALID),
.s_axil_bready(s_axil_0_2_BREADY),
.s_axil_bresp(s_axil_0_2_BRESP),
.s_axil_bvalid(s_axil_0_2_BVALID),
.s_axil_rdata(s_axil_0_2_RDATA),
.s_axil_rready(s_axil_0_2_RREADY),
.s_axil_rresp(s_axil_0_2_RRESP),
.s_axil_rvalid(s_axil_0_2_RVALID),
.s_axil_wdata(s_axil_0_2_WDATA),
.s_axil_wready(s_axil_0_2_WREADY),
.s_axil_wstrb(s_axil_0_2_WSTRB),
.s_axil_wvalid(s_axil_0_2_WVALID));
ssp_combo_channel_2_axis_data_fifo_0_0 axis_data_fifo_0
(.m_axis_tdata(axis_data_fifo_0_M_AXIS_TDATA),
.m_axis_tkeep(axis_data_fifo_0_M_AXIS_TKEEP),
.m_axis_tlast(axis_data_fifo_0_M_AXIS_TLAST),
.m_axis_tready(axis_data_fifo_0_M_AXIS_TREADY),
.m_axis_tvalid(axis_data_fifo_0_M_AXIS_TVALID),
.s_axis_aclk(aclk_0_1),
.s_axis_aresetn(stream_rx_ctrl_0_s2mm_resetn),
.s_axis_tdata(stream_rx_ctrl_0_egress_TDATA),
.s_axis_tkeep(stream_rx_ctrl_0_egress_TKEEP),
.s_axis_tlast(stream_rx_ctrl_0_egress_TLAST),
.s_axis_tready(stream_rx_ctrl_0_egress_TREADY),
.s_axis_tstrb(stream_rx_ctrl_0_egress_TSTRB),
.s_axis_tvalid(stream_rx_ctrl_0_egress_TVALID));
ssp_combo_channel_2_axis_data_fifo_1_0 axis_data_fifo_1
(.m_axis_tdata(axis_data_fifo_1_M_AXIS_TDATA),
.m_axis_tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
.m_axis_tlast(axis_data_fifo_1_M_AXIS_TLAST),
.m_axis_tready(axis_data_fifo_1_M_AXIS_TREADY),
.m_axis_tvalid(axis_data_fifo_1_M_AXIS_TVALID),
.s_axis_aclk(aclk_0_1),
.s_axis_aresetn(aresetn_0_1),
.s_axis_tdata(axi_datamover_0_M_AXIS_MM2S_TDATA),
.s_axis_tkeep(axi_datamover_0_M_AXIS_MM2S_TKEEP),
.s_axis_tlast(axi_datamover_0_M_AXIS_MM2S_TLAST),
.s_axis_tready(axi_datamover_0_M_AXIS_MM2S_TREADY),
.s_axis_tvalid(axi_datamover_0_M_AXIS_MM2S_TVALID));
ssp_combo_channel_2_blk_mem_gen_0_0 blk_mem_gen_0
(.addra(xlslice_0_Dout),
.addrb(stream_tx_ctrl_0_desc_if_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(stream_tx_ctrl_0_desc_if_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(stream_tx_ctrl_0_desc_if_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(stream_tx_ctrl_0_desc_if_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(stream_tx_ctrl_0_desc_if_WE));
ssp_combo_channel_2_regfile_0_0 regfile_0
(.clk(aclk_0_1),
.reg_0(regfile_0_reg_0),
.reg_1(regfile_0_reg_1),
.reg_2(regfile_0_reg_2),
.reg_3(regfile_0_reg_3),
.reg_4(regfile_0_reg_4),
.reg_5(regfile_0_reg_5),
.reg_6(regfile_0_reg_6),
.reg_rd_ack(regfile_0_reg_rd_ack),
.reg_rd_addr(axil_reg_if_0_reg_rd_addr[7:0]),
.reg_rd_data(regfile_0_reg_rd_data),
.reg_rd_en(axil_reg_if_0_reg_rd_en),
.reg_rd_wait(regfile_0_reg_rd_wait),
.reg_wr_ack(regfile_0_reg_wr_ack),
.reg_wr_addr(axil_reg_if_0_reg_wr_addr[7:0]),
.reg_wr_data(axil_reg_if_0_reg_wr_data),
.reg_wr_en(axil_reg_if_0_reg_wr_en),
.reg_wr_strb(axil_reg_if_0_reg_wr_strb),
.reg_wr_wait(regfile_0_reg_wr_wait),
.resetn(aresetn_0_1),
.status_0(stream_rx_ctrl_0_status_00),
.status_1(stream_rx_ctrl_0_status_01),
.status_10(ssp_rx_0_status_02),
.status_11(ssp_rx_0_status_03),
.status_12(ssp_rx_0_status_04),
.status_13(ssp_rx_0_status_05),
.status_14(ssp_rx_0_status_06),
.status_15(ssp_rx_0_status_07),
.status_2(stream_rx_ctrl_0_status_02),
.status_3(stream_rx_ctrl_0_status_03),
.status_4(stream_rx_ctrl_0_status_04),
.status_5(stream_rx_ctrl_0_status_05),
.status_6(stream_rx_ctrl_0_status_06),
.status_7(stream_rx_ctrl_0_status_07),
.status_8(ssp_rx_0_status_00),
.status_9(ssp_rx_0_status_01));
ssp_combo_channel_2_regfile_1_0 regfile_1
(.clk(aclk_0_1),
.reg_0(regfile_1_reg_0),
.reg_1(regfile_1_reg_1),
.reg_2(regfile_1_reg_2),
.reg_3(regfile_1_reg_3),
.reg_4(regfile_1_reg_4),
.reg_5(regfile_1_reg_5),
.reg_rd_ack(regfile_1_reg_rd_ack),
.reg_rd_addr(axil_reg_if_1_reg_rd_addr[7:0]),
.reg_rd_data(regfile_1_reg_rd_data),
.reg_rd_en(axil_reg_if_1_reg_rd_en),
.reg_rd_wait(regfile_1_reg_rd_wait),
.reg_wr_ack(regfile_1_reg_wr_ack),
.reg_wr_addr(axil_reg_if_1_reg_wr_addr[7:0]),
.reg_wr_data(axil_reg_if_1_reg_wr_data),
.reg_wr_en(axil_reg_if_1_reg_wr_en),
.reg_wr_strb(axil_reg_if_1_reg_wr_strb),
.reg_wr_wait(regfile_1_reg_wr_wait),
.resetn(aresetn_0_1),
.status_0(stream_tx_ctrl_0_status_00),
.status_1(stream_tx_ctrl_0_status_01),
.status_10(ssp_tx_0_status_02),
.status_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.status_2(stream_tx_ctrl_0_status_02),
.status_3(stream_tx_ctrl_0_status_03),
.status_4(stream_tx_ctrl_0_status_04),
.status_5(ssp_tx_0_tx_data_count),
.status_6(ssp_tx_0_tx_last_count),
.status_7(ssp_tx_0_status),
.status_8(ssp_tx_0_status_00),
.status_9(ssp_tx_0_status_01));
ssp_combo_channel_2_ssp_rx_0_0 ssp_rx_0
(.aresetn(aresetn_0_1),
.clk(aclk_0_1),
.config_00(regfile_0_reg_4),
.config_01(regfile_0_reg_5),
.config_02(regfile_0_reg_6),
.enable(stream_rx_ctrl_0_enable),
.ssp_clk(ssp_clk_0_1),
.ssp_csn(ssp_csn_0_1),
.ssp_data(ssp_data_0_1),
.status_00(ssp_rx_0_status_00),
.status_01(ssp_rx_0_status_01),
.status_02(ssp_rx_0_status_02),
.status_03(ssp_rx_0_status_03),
.status_04(ssp_rx_0_status_04),
.status_05(ssp_rx_0_status_05),
.status_06(ssp_rx_0_status_06),
.status_07(ssp_rx_0_status_07),
.tdata(ssp_rx_0_interface_axis_TDATA),
.tkeep(ssp_rx_0_interface_axis_TKEEP),
.tlast(ssp_rx_0_interface_axis_TLAST),
.tready(ssp_rx_0_interface_axis_TREADY),
.tstrb(ssp_rx_0_interface_axis_TSTRB),
.tvalid(ssp_rx_0_interface_axis_TVALID));
ssp_combo_channel_2_ssp_tx_0_0 ssp_tx_0
(.aresetn(stream_tx_ctrl_0_mm2s_resetn),
.clk(aclk_0_1),
.config_00(regfile_1_reg_4),
.config_01(regfile_1_reg_5),
.ssp_clk(ssp_tx_0_ssp_clk),
.ssp_csn(ssp_tx_0_ssp_csn),
.ssp_data(ssp_tx_0_ssp_data),
.status_00(ssp_tx_0_status_00),
.status_01(ssp_tx_0_status_01),
.status_02(ssp_tx_0_status_02),
.tdata(axis_data_fifo_1_M_AXIS_TDATA),
.tkeep(axis_data_fifo_1_M_AXIS_TKEEP),
.tlast(axis_data_fifo_1_M_AXIS_TLAST),
.tready(axis_data_fifo_1_M_AXIS_TREADY),
.tstrb(1'b1),
.tvalid(axis_data_fifo_1_M_AXIS_TVALID));
ssp_combo_channel_2_stream_rx_ctrl_0_0 stream_rx_ctrl_0
(.clk(aclk_0_1),
.cmd_tdata(stream_rx_ctrl_0_cmd_TDATA),
.cmd_tready(stream_rx_ctrl_0_cmd_TREADY),
.cmd_tvalid(stream_rx_ctrl_0_cmd_TVALID),
.config_00(regfile_0_reg_0),
.config_01(regfile_0_reg_1),
.config_02(regfile_0_reg_2),
.config_03(regfile_0_reg_3),
.egress_tdata(stream_rx_ctrl_0_egress_TDATA),
.egress_tkeep(stream_rx_ctrl_0_egress_TKEEP),
.egress_tlast(stream_rx_ctrl_0_egress_TLAST),
.egress_tready(stream_rx_ctrl_0_egress_TREADY),
.egress_tstrb(stream_rx_ctrl_0_egress_TSTRB),
.egress_tvalid(stream_rx_ctrl_0_egress_TVALID),
.enable(stream_rx_ctrl_0_enable),
.ingress_tdata(ssp_rx_0_interface_axis_TDATA),
.ingress_tkeep(ssp_rx_0_interface_axis_TKEEP),
.ingress_tlast(ssp_rx_0_interface_axis_TLAST),
.ingress_tready(ssp_rx_0_interface_axis_TREADY),
.ingress_tstrb(ssp_rx_0_interface_axis_TSTRB),
.ingress_tvalid(ssp_rx_0_interface_axis_TVALID),
.rst_n(aresetn_0_1),
.s2mm_err(axi_datamover_0_s2mm_err),
.s2mm_resetn(stream_rx_ctrl_0_s2mm_resetn),
.status_00(stream_rx_ctrl_0_status_00),
.status_01(stream_rx_ctrl_0_status_01),
.status_02(stream_rx_ctrl_0_status_02),
.status_03(stream_rx_ctrl_0_status_03),
.status_04(stream_rx_ctrl_0_status_04),
.status_05(stream_rx_ctrl_0_status_05),
.status_06(stream_rx_ctrl_0_status_06),
.status_07(stream_rx_ctrl_0_status_07),
.status_tdata(axi_datamover_0_M_AXIS_S2MM_STS_TDATA),
.status_tkeep(axi_datamover_0_M_AXIS_S2MM_STS_TKEEP),
.status_tlast(axi_datamover_0_M_AXIS_S2MM_STS_TLAST),
.status_tready(axi_datamover_0_M_AXIS_S2MM_STS_TREADY),
.status_tstrb({1'b1,1'b1,1'b1,1'b1}),
.status_tvalid(axi_datamover_0_M_AXIS_S2MM_STS_TVALID));
ssp_combo_channel_2_stream_tx_ctrl_0_0 stream_tx_ctrl_0
(.clk(aclk_0_1),
.cmd_tdata(stream_tx_ctrl_0_cmd_TDATA),
.cmd_tready(stream_tx_ctrl_0_cmd_TREADY),
.cmd_tvalid(stream_tx_ctrl_0_cmd_TVALID),
.config_00(regfile_1_reg_0),
.config_01(regfile_1_reg_1),
.config_02(regfile_1_reg_2),
.config_03(regfile_1_reg_3),
.desc_addr(stream_tx_ctrl_0_desc_if_ADDR),
.desc_clk(stream_tx_ctrl_0_desc_if_CLK),
.desc_rdata(stream_tx_ctrl_0_desc_if_DOUT),
.desc_wdata(stream_tx_ctrl_0_desc_if_DIN),
.desc_we(stream_tx_ctrl_0_desc_if_WE),
.mm2s_err(axi_datamover_0_mm2s_err),
.mm2s_resetn(stream_tx_ctrl_0_mm2s_resetn),
.rst_n(aresetn_0_1),
.status_00(stream_tx_ctrl_0_status_00),
.status_01(stream_tx_ctrl_0_status_01),
.status_02(stream_tx_ctrl_0_status_02),
.status_03(stream_tx_ctrl_0_status_03),
.status_04(stream_tx_ctrl_0_status_04),
.status_05(ssp_tx_0_tx_data_count),
.status_06(ssp_tx_0_tx_last_count),
.status_07(ssp_tx_0_status),
.status_tdata(axi_datamover_0_M_AXIS_MM2S_STS_TDATA),
.status_tkeep(axi_datamover_0_M_AXIS_MM2S_STS_TKEEP),
.status_tlast(axi_datamover_0_M_AXIS_MM2S_STS_TLAST),
.status_tready(axi_datamover_0_M_AXIS_MM2S_STS_TREADY),
.status_tstrb(1'b1),
.status_tvalid(axi_datamover_0_M_AXIS_MM2S_STS_TVALID));
ssp_combo_channel_2_xlslice_0_0 xlslice_0
(.Din(axi_bram_ctrl_0_bram_addr_a[13:0]),
.Dout(xlslice_0_Dout));
endmodule

257
ssp_2/src/ssp_combo_channel_2_axi_bram_ctrl_0_0/ssp_combo_channel_2_axi_bram_ctrl_0_0.xci Normal file
View File

@@ -0,0 +1,257 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "ssp_combo_channel_2_axi_bram_ctrl_0_0",
"cell_name": "axi_bram_ctrl_0",
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
"ip_revision": "9",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ECC_TYPE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"USE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "ssp_combo_channel_2_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ],
"BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ],
"MEM_DEPTH": [ { "value": "4096", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ],
"C_MEMORY_DEPTH": [ { "value": "4096", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BRAM_ADDR_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_ADDR_WIDTH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
"C_READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "artix7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7a200t" } ],
"PACKAGE": [ { "value": "fbg484" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "9" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
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}
}
}
}
}

592
ssp_2/src/ssp_combo_channel_2_axi_datamover_0_0/ssp_combo_channel_2_axi_datamover_0_0.xci Normal file
View File

@@ -0,0 +1,592 @@
{
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"HAS_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWADDR": [ { "physical_name": "m_axi_s2mm_awaddr" } ],
"AWBURST": [ { "physical_name": "m_axi_s2mm_awburst" } ],
"AWCACHE": [ { "physical_name": "m_axi_s2mm_awcache" } ],
"AWID": [ { "physical_name": "m_axi_s2mm_awid" } ],
"AWLEN": [ { "physical_name": "m_axi_s2mm_awlen" } ],
"AWPROT": [ { "physical_name": "m_axi_s2mm_awprot" } ],
"AWREADY": [ { "physical_name": "m_axi_s2mm_awready" } ],
"AWSIZE": [ { "physical_name": "m_axi_s2mm_awsize" } ],
"AWUSER": [ { "physical_name": "m_axi_s2mm_awuser" } ],
"AWVALID": [ { "physical_name": "m_axi_s2mm_awvalid" } ],
"BREADY": [ { "physical_name": "m_axi_s2mm_bready" } ],
"BRESP": [ { "physical_name": "m_axi_s2mm_bresp" } ],
"BVALID": [ { "physical_name": "m_axi_s2mm_bvalid" } ],
"WDATA": [ { "physical_name": "m_axi_s2mm_wdata" } ],
"WLAST": [ { "physical_name": "m_axi_s2mm_wlast" } ],
"WREADY": [ { "physical_name": "m_axi_s2mm_wready" } ],
"WSTRB": [ { "physical_name": "m_axi_s2mm_wstrb" } ],
"WVALID": [ { "physical_name": "m_axi_s2mm_wvalid" } ]
}
},
"S_AXIS_S2MM": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_s2mm_tdata" } ],
"TKEEP": [ { "physical_name": "s_axis_s2mm_tkeep" } ],
"TLAST": [ { "physical_name": "s_axis_s2mm_tlast" } ],
"TREADY": [ { "physical_name": "s_axis_s2mm_tready" } ],
"TVALID": [ { "physical_name": "s_axis_s2mm_tvalid" } ]
}
},
"S_AXIS_S2MM_CMD": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_s2mm_cmd_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_s2mm_cmd_tready" } ],
"TVALID": [ { "physical_name": "s_axis_s2mm_cmd_tvalid" } ]
}
},
"M_AXIS_S2MM_STS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_s2mm_sts_tdata" } ],
"TKEEP": [ { "physical_name": "m_axis_s2mm_sts_tkeep" } ],
"TLAST": [ { "physical_name": "m_axis_s2mm_sts_tlast" } ],
"TREADY": [ { "physical_name": "m_axis_s2mm_sts_tready" } ],
"TVALID": [ { "physical_name": "m_axis_s2mm_sts_tvalid" } ]
}
},
"S_AXIS_MM2S_CMD": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_mm2s_cmd_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_mm2s_cmd_tready" } ],
"TVALID": [ { "physical_name": "s_axis_mm2s_cmd_tvalid" } ]
}
},
"M_AXIS_MM2S_STS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_mm2s_sts_tdata" } ],
"TKEEP": [ { "physical_name": "m_axis_mm2s_sts_tkeep" } ],
"TLAST": [ { "physical_name": "m_axis_mm2s_sts_tlast" } ],
"TREADY": [ { "physical_name": "m_axis_mm2s_sts_tready" } ],
"TVALID": [ { "physical_name": "m_axis_mm2s_sts_tvalid" } ]
}
},
"M_AXI_MM2S_ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_MM2S:M_AXIS_MM2S:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "m_axi_mm2s_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "m_axi_mm2s_aclk" } ]
}
},
"M_AXI_MM2S_ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "m_axi_mm2s_aresetn" } ]
}
},
"M_AXI_S2MM_ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_S2MM:S_AXIS_S2MM", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
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}

189
ssp_2/src/ssp_combo_channel_2_axil_reg_if_0_0/ssp_combo_channel_2_axil_reg_if_0_0.xci Normal file
View File

@@ -0,0 +1,189 @@
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189
ssp_2/src/ssp_combo_channel_2_axil_reg_if_1_0/ssp_combo_channel_2_axil_reg_if_1_0.xci Normal file
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@@ -0,0 +1,189 @@
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}
}

188
ssp_2/src/ssp_combo_channel_2_axis_data_fifo_0_0/ssp_combo_channel_2_axis_data_fifo_0_0.xci Normal file
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@@ -0,0 +1,188 @@
{
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184
ssp_2/src/ssp_combo_channel_2_axis_data_fifo_1_0/ssp_combo_channel_2_axis_data_fifo_1_0.xci Normal file
View File

@@ -0,0 +1,184 @@
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}

284
ssp_2/src/ssp_combo_channel_2_blk_mem_gen_0_0/ssp_combo_channel_2_blk_mem_gen_0_0.xci Normal file
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@@ -0,0 +1,284 @@
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}

12
ssp_2/src/ssp_combo_channel_2_ooc.xdc Normal file
View File

@@ -0,0 +1,12 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name clk -period 10 [get_ports clk]
create_clock -name ssp_rx_clk -period 10 [get_ports ssp_rx_clk]
################################################################################

119
ssp_2/src/ssp_combo_channel_2_regfile_0_0/ssp_combo_channel_2_regfile_0_0.xci Normal file
View File

@@ -0,0 +1,119 @@
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119
ssp_2/src/ssp_combo_channel_2_regfile_1_0/ssp_combo_channel_2_regfile_1_0.xci Normal file
View File

@@ -0,0 +1,119 @@
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151
ssp_2/src/ssp_combo_channel_2_ssp_rx_0_0/ssp_combo_channel_2_ssp_rx_0_0.xci Normal file
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@@ -0,0 +1,151 @@
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125
ssp_2/src/ssp_combo_channel_2_ssp_tx_0_0/ssp_combo_channel_2_ssp_tx_0_0.xci Normal file
View File

@@ -0,0 +1,125 @@
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}
}

258
ssp_2/src/ssp_combo_channel_2_stream_rx_ctrl_0_0/ssp_combo_channel_2_stream_rx_ctrl_0_0.xci Normal file
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}

235
ssp_2/src/ssp_combo_channel_2_stream_tx_ctrl_0_0/ssp_combo_channel_2_stream_tx_ctrl_0_0.xci Normal file
View File

@@ -0,0 +1,235 @@
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"component_reference": "xilinx.com:user:stream_tx_ctrl:1.0",
"ip_revision": "2",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BRAM_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BTT_WIDTH": [ { "value": "23", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CMD_WIDTH": [ { "value": "72", "resolve_type": "user", "format": "long", "usage": "all" } ],
"STATUS_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DESC_IDX_WIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "ssp_combo_channel_2_stream_tx_ctrl_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"BUF_ADDR_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"BRAM_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"BTT_WIDTH": [ { "value": "23", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"STREAM_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CMD_WIDTH": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"STATUS_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DESC_IDX_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "artix7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7a200t" } ],
"PACKAGE": [ { "value": "fbg484" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "2" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"clk": [ { "direction": "in" } ],
"rst_n": [ { "direction": "in" } ],
"config_00": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"config_01": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"config_02": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"config_03": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"status_00": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"status_01": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"status_02": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"status_03": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"status_04": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
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"status_06": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"status_07": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"mm2s_err": [ { "direction": "in" } ],
"mm2s_resetn": [ { "direction": "out" } ],
"cmd_tdata": [ { "direction": "out", "size_left": "71", "size_right": "0" } ],
"cmd_tvalid": [ { "direction": "out" } ],
"cmd_tlast": [ { "direction": "out" } ],
"cmd_tkeep": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
"cmd_tstrb": [ { "direction": "out", "size_left": "8", "size_right": "0" } ],
"cmd_tready": [ { "direction": "in", "driver_value": "1" } ],
"status_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
"status_tvalid": [ { "direction": "in" } ],
"status_tlast": [ { "direction": "in", "driver_value": "0" } ],
"status_tkeep": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
"status_tstrb": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
"status_tready": [ { "direction": "out" } ],
"desc_clk": [ { "direction": "out" } ],
"desc_en": [ { "direction": "out" } ],
"desc_we": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"desc_addr": [ { "direction": "out", "size_left": "10", "size_right": "0" } ],
"desc_wdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ],
"desc_rdata": [ { "direction": "in", "size_left": "63", "size_right": "0" } ]
},
"interfaces": {
"cmd": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "9", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "cmd_tdata" } ],
"TSTRB": [ { "physical_name": "cmd_tstrb" } ],
"TKEEP": [ { "physical_name": "cmd_tkeep" } ],
"TLAST": [ { "physical_name": "cmd_tlast" } ],
"TVALID": [ { "physical_name": "cmd_tvalid" } ],
"TREADY": [ { "physical_name": "cmd_tready" } ]
}
},
"status": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "status_tdata" } ],
"TSTRB": [ { "physical_name": "status_tstrb" } ],
"TKEEP": [ { "physical_name": "status_tkeep" } ],
"TLAST": [ { "physical_name": "status_tlast" } ],
"TVALID": [ { "physical_name": "status_tvalid" } ],
"TREADY": [ { "physical_name": "status_tready" } ]
}
},
"mm2s_resetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "mm2s_resetn" } ]
}
},
"rst_n": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "rst_n" } ]
}
},
"clk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "cmd:status", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "ssp_combo_channel_2_clk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "clk" } ]
}
},
"desc_clk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "desc_clk" } ]
}
},
"desc_if": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "master",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"DIN": [ { "physical_name": "desc_wdata" } ],
"EN": [ { "physical_name": "desc_en" } ],
"DOUT": [ { "physical_name": "desc_rdata" } ],
"CLK": [ { "physical_name": "desc_clk" } ],
"WE": [ { "physical_name": "desc_we" } ],
"ADDR": [ { "physical_name": "desc_addr" } ]
}
}
}
}
}
}

53
ssp_2/src/ssp_combo_channel_2_xlslice_0_0/ssp_combo_channel_2_xlslice_0_0.xci Normal file
View File

@@ -0,0 +1,53 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "ssp_combo_channel_2_xlslice_0_0",
"cell_name": "xlslice_0",
"component_reference": "xilinx.com:ip:xlslice:1.0",
"ip_revision": "3",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "ssp_combo_channel_2_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
"DIN_TO": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DIN_FROM": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DIN_WIDTH": [ { "value": "14", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DOUT_WIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"DIN_WIDTH": [ { "value": "14", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DIN_FROM": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DIN_TO": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "artix7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7a200t" } ],
"PACKAGE": [ { "value": "fbg484" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "3" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"Din": [ { "direction": "in", "size_left": "13", "size_right": "0" } ],
"Dout": [ { "direction": "out", "size_left": "10", "size_right": "0" } ]
}
}
}
}

10
ssp_2/xgui/ssp_combo_channel_2_v1_0.tcl Normal file
View File

@@ -0,0 +1,10 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}