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new_project_rtl_template/sim/instantiate_top.sv

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+/*>>>>>>>>>>>>>>>>>>>>>>>THIS FILE IS GENERERATED BY ROBOT >>>>>>>>>>>>>>>>>>>*/ 
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>port declaration>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*add all port here*/                                                            
+/*use "logic" to replace "logic" and "logic" ports*/                            
+/*use "wire" to replace "inout" ports*/                                          
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<port declaration<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+//TODO:                                                                          	
+
+logic clk;
+logic rstn;
+
+logic uart_rx;
+logic uart_tx;
+
+logic [7:0] led;
+
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>logic ports intialization>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/   
+/*initialize all "logic" ports here                                                         
+/*all inputs default as 0,modify if necessary                                               
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<logic ports intialization<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/   
+//TODO:
+/*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>instantiate top most module>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ 
+/*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<instantiate top most module<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/ 
+                                                                                            
+/*do not modify
+*/
+`TOP_ENTITY `TOP_INSTANCE(.*);